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PAGE 1 Introduction to Digital Logic with Laboratory Exercises PAGE 2 This book is licensed under a Creative Commons Attribution 3.0 License Introduction to Digital Logic with Laboratory ExercisesJames FeherCopyright 2009 James Feher EditorInChief: James Feher Associate Editor: Marisa Drexel Proofreaders: Jackie Sharman, Rachel Pugliese For any questions about this text, please email: drexel@uga.edu The Global Text Project is funded by the Jacobs Foundation, Zurich, Switzerland This book is licensed under a Creative Commons Attribution 3.0 License Introduction to Digital Logic with Laboratory Exercises2 A Global Text PAGE 3 Table of ContentsPreface ............................................................................................................................................................... 70. Introduction ............................................................................................................................. 9 1. The transistor and inverter .................................................................................................... 10The transistor .................................................................................................................................................. 10 The breadboard ................................................................................................................................................ 11 The inverter ..................................................................................................................................................... 122. Logic gates .............................................................................................................................. 14History of logic chips ....................................................................................................................................... 14 Logic symbols .................................................................................................................................................. 15 Logical functions ............................................................................................................................................. 163. Logic simplification ................................................................................................................ 19De Morgan's laws ............................................................................................................................................ 19 Karnaugh maps ............................................................................................................................................... 20 Circuit design, construction and debugging .................................................................................................. 244. More logic simplification ....................................................................................................... 27Additional Kmap groupings .......................................................................................................................... 27 Input placement on Kmap ............................................................................................................................ 29 Don't care conditions ...................................................................................................................................... 295. Multiplexer ............................................................................................................................. 32Background on the mux .............................................................................................................................. 32 Using a multiplexer to implement logical functions ...................................................................................... 326. Timers and clocks .................................................................................................................. 37Timing in digital circuits ................................................................................................................................. 37 555 timer ......................................................................................................................................................... 37 Timers ............................................................................................................................................................. 37 Clocks .............................................................................................................................................................. 38 Timing diagrams ............................................................................................................................................. 397. Memory ................................................................................................................................. 44Memory ........................................................................................................................................................... 44 SR latch ........................................................................................................................................................... 44 Flipflops ......................................................................................................................................................... 458. State machines ....................................................................................................................... 49What is a state machine? ................................................................................................................................ 49 State transition diagrams ............................................................................................................................... 50 State machine design ...................................................................................................................................... 51 Debounced switches ........................................................................................................................................ 559. More state machines .............................................................................................................. 57How many bits of memory does a state machine need? ................................................................................ 57 What are unused states? ................................................................................................................................. 5710. What's next? ......................................................................................................................... 64 Appendix A: Chip pinouts ......................................................................................................... 65 Appendix B: Resistors and capacitors ...................................................................................... 69Resistors .......................................................................................................................................................... 69 Capacitors ....................................................................................................................................................... 70 3 PAGE 4 This book is licensed under a Creative Commons Attribution 3.0 License Appendix C: Lab notebook ......................................................................................................... 71 Appendix D: Boolean algebra .................................................................................................... 73 Appendix E: Equipment list ...................................................................................................... 74Digital trainer .................................................................................................................................................. 74 7400 series families ........................................................................................................................................ 75Appendix F: Solutions ............................................................................................................... 76Chapter 1 review exercises .............................................................................................................................. 76 Chapter 2 review exercises .............................................................................................................................78 Chapter 3 review exercises .............................................................................................................................. 81 Chapter 4 review exercises ............................................................................................................................. 87 Chapter 5 review exercises ............................................................................................................................. 90 Chapter 6 review exercises ............................................................................................................................. 95 Chapter 7 review exercises ............................................................................................................................. 98 Chapter 8 review exercises ............................................................................................................................ 101 Chapter 9 review exercises ........................................................................................................................... 104Index .......................................................................................................................................105Introduction to Digital Logic with Laboratory Exercises4 A Global Text PAGE 5 Index of Tables Table 1: NAND table ................................................................................................................... 15 Table 2: NOR table ..................................................................................................................... 15 Table 3: AB + BC ........................................................................................................................ 16 Table 4: XOR table ..................................................................................................................... 17 Table 5: 4 input Kmap .............................................................................................................. 20 Table 6: 2 input Kmap ............................................................................................................. 20 Table 7: 3 input Kmap .............................................................................................................. 20 Table 8: f(A,B,C) ......................................................................................................................... 21 Table 9: g(A,B,C,D) .................................................................................................................... 22 Table 10: h(A,B,C,D) .................................................................................................................. 23 Table 11: h(w,x,y,z) ..................................................................................................................... 23 Table 12: Step 3 .......................................................................................................................... 23 Table 13: Step 2 .......................................................................................................................... 23 Table 14: Step 5 .......................................................................................................................... 23 Table 15: g(a,b,c) ........................................................................................................................ 33 Table 16: g(a,b,c) ........................................................................................................................ 33 Table 17: h(a,b,c,d) ..................................................................................................................... 34 Table 18: h(a,b,c,d) .................................................................................................................... 34 Table 19: NOR SR latch ............................................................................................................. 44 Table 20: NAND SR latch .......................................................................................................... 44 Table 21: JK flipflop .................................................................................................................. 45 Table 22: T flipflop ................................................................................................................... 45 Table 23: D flipflop ................................................................................................................... 45 Table 24: Truth table .................................................................................................................. 51 Table 25: Counter truth table .................................................................................................... 52 Table 26: Q1N(x,Q1,Q0) ............................................................................................................ 53 Table 27: Q0N(x,Q1,Q0) ............................................................................................................ 53 Table 28: Q1N(x,Q1,Q0) = Q1N = x' Q1'Q0' + xQ1'Q0 ............................................................. 58 Table 29: Q0N(x,Q1,Q0) = xQ1'Q0' + x'Q1Q0' ......................................................................... 58 Table 30: Q1N(x,Q1,Q0) = xQ1'Q0' + x'Q0 .............................................................................. 58 Table 31: Q0N(x,Q1,Q0) = xQ1'Q0' + x'Q1 ................................................................................ 58 Table 32: Truth table for 5 state machine ................................................................................ 60 Table 33: Q2N ............................................................................................................................ 60 Table 34: Q1N ............................................................................................................................ 60 Table 35: Q0N ............................................................................................................................ 61 Table 36: Color Codes ................................................................................................................ 695 PAGE 6 This book is licensed under a Creative Commons Attribution 3.0 License About the author and reviewers Author: James FeherJim cu rrently teaches compute r science at McKendree University in Lebanon, Illinois. He is a huge open source softw are proponent. His research focuses on the us e of open source so ftwa re in theareas of hard ware, programming and networking. His hobbie s includ e triathlon, hiking, camping and the use of alternative ene rgy. He lives with his wife and three kids in St. Louis, MIssouri where he built and continues to perfect a solar hot water heating system for his home.Reviewer: Kumud BhandariKumud graduated from McK endree University with degrees in computer science and mathematics. He has worked at internships at the University of Texas and the Massachusetts In stitute of Technology. He currently isemployed as a researcher with Argonne National Laboratory.Reviewer: Andrew Van CampProfessor Van Camp is a retired electronics professor. In addition, he has extensive experience working and consulting in industry. He currently resides in central Missouri where he continues his consulting for industry.Introduction to Digital Logic with Laboratory Exercises6 A Global Text PAGE 7 This book is licensed under a Creative Commons Attribution 3.0 License PrefaceThis lab manual provides an introduct ion to digital logic, starting with simple gates and building up to state machine s. Students should have a solid understanding of algebra as well as a rudimentary understanding of basic ele ctricity including voltage, current, resistance, capacitance, induct ance and how the y relate to direct current circuits. Labs will be built utilizing the following hardware:!breadboards with associated items required such as wire, wire strippers and cutters!some basic discrete components such as transistor s, resistor s and capacitors!basic 7400 series logic chips!555 timer Discrete components will be included only whe n n ecessar y, w ith m ost of t he labs usi ng t he standard 7400 series logic chips. These items are commonly available and can be obtained relatively inexpensively. Labs will include learning objectives, relevant theory, review proble ms, and suggested procedure. In addition to the labs, several appendices of background material are provided. Format for each chapterEach chapter is a combination of the ory followe d by review exercises to be complet ed as traditional homework assignments. F ull s olutions t o all of the review e xercises a re available i n t he last a ppendix. Pr ocedures for labs the n follow that allow the student to imple ment the concepts in a hands on manner. The materials required for the labs were selec ted due to their ready availabi lity at modest cost. While stude nts woul d gain from just reading and completing the review exercises, it is recommended that the proced ures be completed as well. In addition to providing another means reenforcing the material, it helps to develop real world debugging and design skills. This manual concentrates on the basic building blocks of digital electronics: logic gates and memory. It focuses on these items from the ground up. The rea der will first see how logic gates c an be constructe d from transistor s and then how digital logic functions are constructed using those gates. The concept of memory is the n introduced through the c onstruction of an SR latch and then a D flipflop A clock i s created to be used in a ba sic state machine design that aims to combine logic circuits with memory. Target audienceThis text will be geared toward computer science stude nts; however it woul d be appropriate for any students who have the necessary background in algebra and elementary DC ele ctronics. Computer science students learn skills in analysis, de sign and debugging. These skills are also used in the virtual world of programming, where no physical devices are eve r involved. By requiring the assembly and demonstration o f actual circuits, students wil l not only learn about digital logic, but about the intricacies and difficulties that ari se when phys ically implementing their designs as well. Global Text ProjectEducation is the most powerful weapon you can use to change the world Nelson Mandela The goal of this te xt is to allow more students to gain access to this material by providing it in the Creative Commons as well as spe cifying inexpensive materials to be use d in the labs. For this reason the author chose toIntroduction to Digital Logic with Laboratory Exercises7 A Global Text PAGE 8 Preface work with the Global Text project to develop this text. The Global Text Project will create open content electr onic textbo oks that will be freely available from a websit e. Distribution will also be possible via paper, CD, or DV D. The goal of the Global Text Project initially is to focus on content develop ment and Web distribution, and work with relevant authorities to facilitate dissemination by other means whe n bandwidth is unavail able or inadequate. The goal is to make textbooks available to the many who cannot afford them.AcknowledgmentsA work such as this wou ld not be possible without the hel p of many. First, I would like to thank the Global Text Project for their vision of providing electr onic textbooks for free to eve ryone. Marisa Drexel, Associate Editor at the Global Text Project provided countless suggestions and helpf ul hints for the documen t and for the creation of the document using Ope nOffice. Andrew Van Camp II, retired profes sor of ele ctronics provided excell ent suggestions for technical review of the content. Kumud Bhandari, currently a research aide at Argonn e National Labora tory, provided also provided technical review of the material. My studen ts Evan VanS coyk, Samantha Barnes, and Ben York all provided helpfu l corrections and review as we ll as countless diagrams found in the document. I would like tp thank all of the countless ope nsource developers who produced such fine software as GNU/L inux, OpenOffice, the Gimp, and Dia which were all use d to create this document. I am grateful to McKendree University for providing support in the form of a sabbatical to allow me to complete this work. And I certainly wish to thank Sandy who provided excellent review sugge stions, support and an extremely patient ear when I ran into trouble trying to incorporate a new feature from OpenOffice or attempted edit a particularly tricky graphic. 8 PAGE 9 This book is licensed under a Creative Commons Attribution 3.0 License 0. IntroductionIt is nearly impossible to find a part of society that has not been touched by digital ele ctronics Obvious applications such as computers, tel evisions, digital video reorders and countle ss other consumer elect roni cs wou ld not be possible without them. The Internet is run on a system of computers and routing equipment built with digital e lectronics. Y et even outsi de o f some of t hese obvious app lications we f ind that our cars and utilitarian home appliances such as microwaves, washe rs, dryers, coffee makers and even refrigerators are all increasingly being design ed with digi tal electronic c ontrols. You likely carry some sort of device designed with t hem with you nearly all your waking hours whe ther it is a watch, cell phone, MP3 player or PDA. Indeed, digital electronic s provide the foundation upon which we build the infrastructure of modern society. You no doubt have heard stories about some of the first computers. Machines built with mechanical relays and vacuum tubes that filled e ntire rooms. In the 1940s John B ardeen, Walter Brattain and William Shockley d eveloped the first transistor; it allowed computers to be built cheaper, smaller and more reliable than ever before. The integr ated circuit, a single package with several transistors along with other circuit compone nts, was developed in the late 1950s by Jack Kilby at Texas Instrum ents. This hel ped to further advance the digital revolut ion. Advances then became so common that in the 1960s Gordon Moore, a founder of Intel, proposed his famous law stating that the capacity o f computers we use would double every two year s. This observat ion has held up s ince then, even being amended to a doubling every eighteen months. The quad core microprocessors of today contain millions of components, but the basic building blocks are digital logic functions combined with memory. Despite the fact that many of the se de vi ces are tremendously complex and require vast amounts of engineering in their de sign, they all share the ubiquitous bit as their fundamental unit of data. In essence it all starts with TRUE and FALSE or 0 and 1. And so the next chapter starts with the simplest of logic de vi ces, the inv erter, built with a single transistor. You then continue your journey into the world of digital ele ctronics by examining the NAND and NOR gates. Remember, the d igital revolution woul d not be possible without these simple devices. Introduction to Digital Logic with Laboratory Exercises9 A Global Text PAGE 10 This book is licensed under a Creative Commons Attribution 3.0 License 1. The transistor and inverterLearning objectives!Use the digital trainer and breadboard .!Assemble a circuit.!Build a logic circuit with discrete components.The transistorA transistor is a threeterminal device that can be used as an amplifier or as a switc h. When the transistor i s used as an amplifier, it is working in analog mode When it is being used as an electron ic switc h, it is functioning in digital mode. The transistor will only b e used in digital mode i n the se labs, which means the transistor will either be on or off. The terms ground, low, zero, zero volts, open switch, and dark lamp are all equivalent to the boolean value false. Likewise five volts, high, one, closed switch, and lit lamp (LED), are equivalent to the boolean value true. We will use false (F or 0) and true (T or 1) when speaking of the logical states in this manual. Modern computers contain millions of transistor s combined together in digital mode to create advanced circuits. Transistors are three pin de vices that are similar to va lves fo r c ontrolling e lectricity. The amount of current that can flow bet ween the colle ctor and emitter is a function of the current flowing through the base of the transistor If no current is flowing through the base of t h e transistor n o c u r r e n t w i l l f l o w t h r o u g h t h e collector and emitter. With the transistor operat ing in d i g ital m o de it wil l b e c o n fig ure d t o car r y the maximum (if on) or minimum (if off) amount of current from the collector t o the emi tter that the circuit will allow. The transistor u sed in this lab, the pn2222 or 2n2222, i s an NPN, bipolar junction transistor which is sometimes referred to as a BJT. Other typ es of transistor s exist, and while they differ in how they function, they are used in a similar manner in digital circuits. In this lab, a single transistor will be used to create an inverter The principles used to build this inverter could be applied to othe r circuits with other typ es of transistor s. P inouts of the two types of transistor s most likely to be used in these labs are shown in Exhibit 1.1 .Introduction to Digital Logic with Laboratory Exercises10 A Global Text Exhibit 1.1 : Common NPN transistors PAGE 11 1. The transistor and inverterThe breadboardIn order to build the circuit, a digita l design kit that contains a powe r sup ply, switches for input, light emitt ing diode s (LEDs), and a breadboard will be used. Make sure to follow your instructor's safety instructions when assembling, deb ugging, and observing your circuit. You may also need other items for your lab such as: logic chips, wire, wire cutters, a transistor etc. Exhibit 1.2 shows a common breadboard while Exhibit 1.3 s hows how each set of pins are tied tog et her electroni cally. Exhibit 1.4 shows a fairly complex circuit built on a breadboard For these labs, the highest voltage used in your designs will be five volts or +5V and the lowest will be 0V or ground. A few words of caution regarding the use of the breadboard :!Keep the power off when wiring the circuit.!Make sure to keep things neat, as you can tell from Exhibit 1.4 it is easy for designs to get complex and as a result become difficult to debug.!Do not strip more insulation off of the wires used than is necessary. This can cause wires that are logically at different levels to accidentally touch each other. This creates a short circuit.!Do not push the wires too far into each hole in the breadboard as this can cause two different problems.!The wire can be pushed so far that only the insulation of the wire comes into contact with the breadboard causing an open circuit.!Too much wire is pushed into the hole; it curls under and ends up touching another component at a different logical level. This causes a short circuit.!Use the longer outer rows for +5V on one side and ground on the other side.!Wire power to the circuit first using a common color (say red) for +5V and another (black) for ground. 11 Exhibit 1.3 : Common connections PAGE 12 This book is licensed under a Creative Commons Attribution 3.0 License !Always make sure to have a clearly documented circuit diagram before you start wiring the circuit.The inverterT h e inverter somet imes referred to as a NOT gate, is a simple digital circuit requiring one transistor and two resistor s. The circuit should be connecte d as in Exhibit 1.5 Make sure to start with a neat diagram in your lab noteboo k before you start constructing your circuit! The input i s connected to a switch and the outp ut connecte d t o an LED. The two resistor s are current limiting resistor s and are sized to insure that the circuit operates in digital mode. If the inverter circuit is altered slightly with the addition of another transistor placed in series with the current one, it results in one more input and the creation of a NAND gate. Likewise, if another transistor is added in parallel with the transistor in the inverter circuit a NOR ga te can be built. These two gates are discu ssed at greater length in the next chapter.Review exercises1. Sketch your breadboard Make sure to indicate which portions of the board are electrically connected in common. 2. Construct a truth table for an inverter with x being the input and !x being the output. 3. Using the color code s, determine the value of each of the resistors. Hint: You may nee d to review Appendix B if you are unfamiliar with using resistor s. (a) red, orange, red (b) brown, black, orange (c) orange, orange, orange (d) brown, black, green 4. What is the symbol used for electrical ground or zero volts?Introduction to Digital Logic with Laboratory Exercises12 A Global Text Exhibit 1.4 : Complex circuit Exhibit 1.5: Inverter circuit PAGE 13 1. The transistor and inverter 5. Construct a truth table for a NAND gate. 6. Construct a truth table for a NOR gate.Procedure1. Write the prelab in your lab notebook for all the circuits required in the steps that follow. 2. Obtain instructor approval for your prelab. 3. Draw a diagram of the inverter circuit. 4. With the power off on your digital trainer, construct your inverter Upon completion of the circuit, you may wish to have your instructor examine it before turning the power on. 5. Turn power on for your circuit and verify the proper operation of the inverter 6. Demonstrate the proper operation of the inverter for your instructor. 7. Using a 7404 series logic chip, connect one of the inverter s to demonstrate its operation. Note that Appendix A contains descrip tions of the 7400 serie s chips use d in the labs, including the 7404 inverter chip.Optional exercises1. Draw a diagram of a NAND inverter circuit using two NPN transistor s. 2. Construct the NAND circuit. 3. Verify proper operation of the NAND gate. 4. Demonstrate the proper operation of the NAND for your instructor. 13 PAGE 14 This book is licensed under a Creative Commons Attribution 3.0 License 2. Logic gatesLearning objectives!Use 7400 series chips in designing digital logic functions.!Draw complete circuit diagrams.!Construct and debug digital logic circuits using 7400 series chips.History of logic chipsLogic gates could be constructed from transistor s and resistor s just as the inverter was constructe d in the last lab. However, using discrete transistor s to build logic gates can be time consuming and prone to problems as increasing the number of connections also increases the possible points of failure. Before the advent of the transistor and today in certain industrial applica tions, logic gates are created using mechanical relays. Mechanical device s suffer from similar problems along with the added complication that such devices generally cannot be switched from one state to another quickly enough for modern comput er applications. The introducti on of the integrated circuit in the late 1950s aimed at placing many individual circuit components in a single package that had all of t he connect ions selfcontained in silicon. This revolutionized the comp uting ind ustry a nd has l ed t o C PUs today that contain millions of components in a single chip. You will use 7400 serie s logic chips in this manual. This series of chips has been manufactured since the 1960s. These chips were used to design and build computers during that time; however, they are rarely used i n co mputers built today. Des pite t his, they still have many uses (i n addition to just teachi ng studen ts digital logic). They are still produced, easy to obtain and are fairly inexpensive. The chips come in variou s packages, but the package use d in these labs is a dual inline package, otherwise know as a DIP as shown in Exhibit 2.1 In order to determi ne the polarity of the chip, a notch is put on one side of the chip. From a top view, pin one is on the left of the notch with other pins numbered sequentially in a counter clock wise manner. Chips may also have a dot placed near pin one. Pinouts of the chips that will be used in the labs can be found in Appendix A. Chips i n t he 7 400 fam ily a re constructe d u sing a variety of different circuit configurations t hat all have d iffere nt properti es. Some utilize BJT and others, fie ld ef fe ct transistor s (FETs). The differe nt series (C, HC, L, S, LS, et c. within the 7400 family) are de signed with such considerations as the nee d for low power consumption, switching spee d, or r eliability under s tressful e nvironments th at might be incurred in milit ary a pplications. Consult Appe ndix E for families that are appropriate for these labs.Introduction to Digital Logic with Laboratory Exercises14 A Global Text Exhibit 2.1 : 7400 NAND DIP PAGE 15 2. Logic gatesLogic symbolsAs mentioned in the previous lab, NAND and NOR ga tes can be constructe d with fewer compone nts than AND and OR gates. For this reason, the inverter NAND and NOR m ake up four of the seven chips used in all of the labs. Symbols used to represent the NAND NOR AND, OR and inverter or NOT a re provided along with t he truth table s for the NAND and NOR The truth table s have representing false and r epresenting true. A circuit that can be used to create a NAND gate using two transistor s is shown in Exhibit 2.7. Circuit configurations for NAND gates provided by the 7400 series chips, while logically equivalent, vary from this design. Exhibit 2.2: NAND Exhibit 2.3 : NOR Exhibit 2.4 : Inverter A B Y 0 0 1 0 1 1 1 0 1 1 1 0Table 1: NAND table A B Y 0 0 1 0 1 0 1 0 0 1 1 0Table 2 : NOR table Exhibit 2.5 : AND Exhibit 2.6 : OR Exhibit 2.8 : A' AND B Notice that only the small circle is use d to indicate the inver sion of the AND to produce the NAND instead of using the full inverter symbol in Exhibit 2 .2 This shorthand is often used at the input of a gate shown in Exhibit 2.8 which is equivalent to (A' AND B). Since the NAND gate is used more often, how do you obtain a simple AND or OR gate? One way woul d obviously be to simply combine a NAND gate along with an inverter as in Exhibit 2. 9 While this works, as each chip contains more than one gate, if an extra NAND is available, it may be more advantageous to use a spare gate rather than to use an entirely new chip as in Exhibit 2.10 15 Exhibit 2.7 : NAND circuit PAGE 16 This book is licensed under a Creative Commons Attribution 3.0 License Exhibit 2.9 : NAND inverter yields AND Exhibit 2.10 : NAND NAND to yield ANDLogical functionsExhibit 2.11 demonstrates how to implement a simple logical expression using the gates provided. Make sure to use only those gates that are provided in your kit when designing your circuit. This diagram impleme nts the function f(A,B,C) = AB + BC. Since there are three inputs to this function, there are eight poss ible logical input conditions as shown in the truth table When building a logical circuit, it is important to document the circuit diagram as shown above. However, even this diagram could be made cle arer for those attemp ting to build and deb ug the circuit. Exhibit 2.12 y ield s a much more detailed description of how the circuit should be built. You should include a diagram for every circuit that you build in your lab notebook and you should follow the format in Exhibit 2.12 Let us examine the typ e of information contained here. First, chips are labeled as IC1, IC2 and IC3. Then a legend is included that specifies the type of chip for each of the IC or integrated circuits. The IC numbers should appear in the order that they will appear in your breadboard from left to right or top to bottom, d e p e n d i n g u p o n h o w t h e breadboard i s configured in your digital trainer. Second, the pins use d for each connection on the chip are also given, which makes connecting t h e c i r c u i t p o s s i b l e w i t h o u t h a v i n g t o continually consult the datashee t for that logic chip. Third, the switche s and LEDs are labeled in the order that they are use d forIntroduction to Digital Logic with Laboratory Exercises16 A Global Text A B C f 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1Table 3 : AB + BC Exhibit 2.11 : AB + BC Exhibit 2.12: Detailed wiring diagram for AB+BC PAGE 17 2. Logic gates the respective inputs and outputs. All of this makes it much easier to construct and demonstrate the circuit. But above all, the greatest benefit comes if the circuit does not work and nee ds to be debugg ed! In this case, with all of the pins clearly labeled on your diagram, it is much easier for someone to examine your circuit, compare it to your diagram, trace the various connections and hopefully find and correct any problems in the circuit. LAB NOTEBOOK TIP: In addition to the circuit diagram always put a truth table i n your lab notebook to make it easier to debug and test the operation of your circuit. This circuit wou ld require three diff erent 7400 series logic chips and ten different connections, yet if de signed with individual transistor s using the inverter from the last lab, as we ll as the NAND circuit shown in Exhibit 2.7 this woul d take nine different transistor s, fifteen resistor s, and many more connections than if just the chips were used. It is no wonder that the de crease in complex ity of digital circuits that followed the introduct ion of the 7400 series chips led to a revolution in the computing industry! Let us examine one more simple circuit. This one is use d to impleme nt an exclusive or (XOR ), which is represente d by the symbol i n logical expres sions. The truth table for A XOR B follows along with the g ate used to represent it in circuit diagram s. As no XOR chip is provided in the kit, in order to implement this circuit, the XOR must be built by examin ing the truth table to find the resulting logical function, A'B + AB'. The circuit diagram for the XOR is shown in Exhibit 2.14 Remember, a diagram s uch a s this should be included i n y our lab manual t o ease construction and debugging of the circuit A B 0 0 0 0 1 1 1 0 1 1 1 0Table 4 : XOR table Exhibit 2.13 : XOR Exhibit 2.14 : Circuit diagram for XOR We will discuss how to build more complicated circuits in the next chapter, as well as how to logically simplify the functions with Boolean algebra. Both circuits design ed in this chapter can be simplified significantly with the use of De Morgan's law, also discussed in the next chapter. 17 PAGE 18 This book is licensed under a Creative Commons Attribution 3.0 License Review exercises1. If a logic function has three inputs, how many rows must the truth table have to contain all possible states? Justify your answer. 2. Repeat the last problem for five inputs. 3. For the following functions, construct a truth table and draw a circuit diagram. 1. y(A,B) = (AB)' + B' 2. y(A,B,C) = (A + B)' C 3. y(A,B,C) = (AC)' + BC 4. y(A,B,C) = (A B)C' 5. y(A,B) = A' + B 6. y(A,B,C) = ((A+B)'(B+C)')' 1. For 3(e) of the previous exercise, design the circuit using 7400 series chips listed in Appendix A. Label the pinouts on the circuit diagram. Make sure to label all of the pinouts, just as in Exhibit 2.14 2. Repeat exercise 4 using 3(f).Procedure1. Write the prelab in your lab notebook for all circuits required in the steps that follow. 2. Obtain instructor approval for your prelab. 3. Assemble one single NAND gate from a 7400 chip and verify its operation. 4. Assemble one single NOR gate from a 7402 chip and verify its operation. 5. Build the circuit required for Exercise 4 from the review exercises. Make sure to have your instructor verify that your circuit works correctly before moving on. 6. Build the circuit required for Exercise 5 from the review exercises.Optional procedure1. Design, construct, and verify the operation of the circuit from Exercise 5 using only NAND gates.Introduction to Digital Logic with Laboratory Exercises18 A Global Text PAGE 19 This book is licensed under a Creative Commons Attribution 3.0 License 3. Logic simplificationLearning objectives!Use reduction techniques to obtain minimal functional representations.!Design minimal three and four input logical functions.!Build and debug three and four input logical functions.De Morgan's law sAs you observed in the previous lab, managing the number of connections (or wires) i n y our circuit can become a challenge. This challenge seems to increase exponentially as the number of components in the circuit increases. In order to keep your breadboard a s neat as possible and your de sign as simplified a s poss ible it is often advanta geous to spen d time examining the logical function for ways to reduce the complex ity of the final design. Reducing the number of gates in a circuit will generally lead to a reduction in the number of connections, resulting in a simpler circuit. Designs with fe wer connections and parts have fe wer possible points of failure. Less complex circuits are generally easier and cheaper to build and debug. In this chapter techniques will be introduce d that can help to implement complex circuits in the least complex manner possible. It is often possi ble to implement logical functions correctly in many diff erent ways. The first step in obtaining a logically minimal expre ssion should be a clear understanding of the rules of Boolean algebra listed in Appendix D. De Morga n's laws in particular can be very help ful whe n attempting to si mplify circuit design. De Morg an's laws are listed below. (AB)' = A' + B' (A+B)' = A'B' Given these two equations, it is easy to see the alternate symbols that are sometimes used for the AND and OR gates listed in Exhibit 3.1 and Exhibit 3.2 Applying De Morgan's law s to the functions listed yields the following. (A' + B')' = (AB')' = AB (A'B')' = ((A + B)')' = A + B Exhibit 3.1 : Alternate OR symbol Exhibit 3.2 : Alternate OR symbol An example of using De Morgan's laws for simplification can be found by examining the logical function: AB + BC from the previous chapter. This function can actually be implemented with just three NAND gates and one 7400 chip. Examining the equation AB + BC below and applying De Morgan's law demonstrates that the expression can be implemented with only NAND gates. AB + BC = ( (AB + BC)' ) Double Negative = ( (AB)' (BC)' )' De Morgan's lawIntroduction to Digital Logic with Laboratory Exercises19 A Global Text PAGE 20 3. Logic simplification Notice that the first expres sion exactly matches the function that was built in the previous chapter using two NAND s, one NOR and three inverter s. The new circuit shown in Exhibit 3. 3 i mplements the same express ion with just three NAND gate s. This result s in a design using only one 7400 series chip and fe wer connections that still yields the same result. Des igns with fewer chips and wires generally take les s time to build, resulting in less expen sive, more robust circuits. Similarly, the circuit that imple ments the XOR from the last chapter could be built wi th j us t NAND gate s, however as five gates wou ld be required, it still would use two chips, one 7400 and a 7404.Karnaugh map sKarnaugh maps or Kmap s for short, provide another means of simplifying and optimizing logical expres sions. This is a graphical te chnique that utilizes a sum of product (SOP) form. SOP forms combine terms that have been ANDed togethe r that then get ORed tog et h er. This format lends itself to the use of De Morgan's law which allows the final result to be built with only NAND gates. The Kmap i s best used with logical functions with four or less input variables. As the te chnique generally become s unwield y with more than four inputs, other means of optimization are generally used for expression s of this comple xity. While it can be more instructive for students to u s e Boolean algebra reduct ion techniques, when minimizing gate circuits using Boolean algebra; it is less obvious for students to recognize whe n t hey have reached the s implest circuit configuration. One of the a dvantages o f u sing Kmap s for reduction is that it is easier to see when a circuit has been fully simplifie d. Another advantage is that using Kmap s leads to a more structured process for minimization. In order to use a Kmap the truth table for a logical expression is transferred to a Kmap grid. The grid for two, three, and four i nput expressions a re provi de d in the table s below E ach cell corresponds to one row in a truth table or one given state in the logic al expression. The order of the items in the grid is not random at all; the y are set so that any adjacent cell differs in value by the change in only one vari able. Because of this, ite ms can be grouped tog ether easily in rectangular blocks of two, four, and eigh t to fin d t he minimal number of grouping s th at can cover the entire expression. Note that diagonal cell s require that the value of more than two inputs change, and that they also do not form rectangles. A'B'00A'B01AB11AB'10C'D'00C'D01CD11CD'10Table 5 : 4 input Kmap 20 Exhibit 3.3 : AB + BC (NANDS only) A'0A1B'0B1Table 6 : 2 input Kmap A'B'00A'B01AB11AB'10C'0C1Table 7 : 3 input Kmap PAGE 21 This book is licensed under a Creative Commons Attribution 3.0 License Examine t he ex pression f(A,B,C ) = ABC + ABC' + A'BC + A'BC '. As liste d, it requires four threeinput AND gates, one fourinput OR gate and several inverter s. The truth table is copied over to the eight cell Kmap below. Notice the squar e of ones in the center of the Kmap These cells all share the fact that the y are true when B is true. And indeed, the expressions shown below are equivalent. ABC + ABC' + A'BC + A'BC' = AB(C + C') + A'B(C + C') Distributive Property = AB + A'B C + C' is always true = (A + A')B Distributive Property = B A + A' is always true Of course, implementing the logical expression B is much simpler than the previous expression! Although rules of logic applied above yield the same result, it is often much easier to note the groupings that result in minimal expressions using the graphical representation of the Kmap Let us examine the equation g(A,B, C,D) given in the truth table in Table 6 with the associated Kmap The expres sion contains three diff erent terms: A'B', AC, and ABC'D circled in Exhibit 3.5. However, this is not the minimal expression because not all of the largest possible groupings are included. In order to obtain the largest groupings, it is often necessary to overlap some of the terms. This just causes certain te rms to be included in more than one grouping as shown in Exhibit 3.6. Notice term ABCD which is actually included in two different groupings, ABD and AC, which is perfectl y acceptable. Using the new groupings, we obtain the minimal SOP express ion g(A, B,C,D) = A'B' + AC + ABD. This expres sion contains the same number of groupings or product s, but one less term in one of the products. In this case ABC'D from Exhibit 3.5 is replaced with ABD in Exhibit 3.6 y ielding a simpler expression. While other tech niques exist for finding minimal expre ssions, with some practice, the Kmap can be used effectively for expressions with four or less inputs. Not select ing the largest grouping is a very common error to those just beginning to use Kmaps. Remember, always select the largest grouping possible, even if it results in some terms being double covered. Larger groupings result in simpler expressions.Introduction to Digital Logic with Laboratory Exercises21 A Global Text A B C f 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 Table 8 : f(A,B,C) Exhibit 3.4: Kmap of f(A,B,C) PAGE 22 3. Logic simplification In summary, the procedure for using Kmap s to find minimal logical expressions is given below. 1. Construct the Kmap c orresponding to the truth table 2. Circle any 1 that is NOT adjacent (isolated) to any other 1. 3. Find any 1 that is adjacent to only one othe r 1. Circle these pairs, even if one in the pair has already been circled. 4. Circle any group of eight (octet), even if a 1 in the group has already been circled. 5. Circle any group of four (quad) that contains one or more one 1 that is not already circled. 6. Make sure that every 1 is circled. 7. Form the OR sum of the te rms generated by each grouping. The following example goes through all the steps in order to find the minimal expression for h(A,B,C,D). First, the truth table given in Table 8 is transcribed to fit into the Kmap given in Table 5 22 A B C D g0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1Table 9 : g(A,B,C,D) Exhibit 3.5 : Kmap of g(A,B,C,D) Exhibit 3.6: Kmap of g(A,B,C,D) PAGE 23 This book is licensed under a Creative Commons Attribution 3.0 License In step 2, above, the 1 in the bottom right is shaded. In step 3, to the left, the pair of two 1s in the second column is shaded. Note that the botto m ite m A'BCD dictates that this group is circled. The top item, A'BC'D has many different adjacent elem ents, but the first 1 only has one adjacent element. For ste p 4, no groups of eight exist, so there is no table. For step 5, two groups of four exist, C'D and BC'. Note that both of these groupings cover elements already c overed from step 2 and that both share the group of two, BC'D. This overlap is shaded in green. This is not only perfectly acceptable, but required to obtain the minimal expression. Now, all of the 1s are covered, yielding the minimal solution. h(A,B,C,D) = AB'CD' + A'BD + BC' + C'DIntroduction to Digital Logic with Laboratory Exercises23 A Global Text A B C D g0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0Table 10 : h(A,B,C,D) A'B'00A'B01AB11AB'10C'D'000 1 1 0C'D011 1 1 1CD110 1 0 0CD'100 0 0 1Table 11: h(w,x,y,z) A'B'00A'B01AB11AB'10C'D'000 1 1 0C'D011 1 1 1CD110 1 0 0CD'100 0 0 1Table 12 : Step 3 A'B'00A'B01AB11AB'10C'D'000 1 1 0C'D011 1 1 1CD110 1 0 0CD'100 0 0 1Table 13 : Step 2 A'B'00A'B01AB11AB'10C'D'000 1 1 0C'D011 1 1 1CD110 1 0 0CD'100 0 0 1Table 14 : Step 5 PAGE 24 3. Logic simplificationCircuit design, construction and debuggingWhile these techniques are useful in minimizing the logical expression, ultimately the circuits still need to be constructed. As the complexity of the circuits increases, it is important to note some of the techniques that can be useful in building a complete working circuit. DESIGN TI P: The time spen t in the design stage can pay huge dividends later! Mistakes made at the beginning of the design phase carry through the entire process and can consume countless hours trying to debug the final product.!Start by making sure that the circuit minimization was correct and copied in your lab notebook. The truth table is helpful when testing the final circuit. Building the wrong circuit serves no purpose at all.!Verify that the pinouts selected are proper for each gate and chip; these are helpful when debugging as well as when building the circuit. Again, time spent here helps cut down on the construction and debugging later.!Remember the tips given in Chapter 1 regarding the use of the breadboard .!Keep connecting wires neatly and avoid unnecessarily long loops of wire, yet do not spend excessive time cutting wires that are exactly the proper length between spans. It may feel like a work of art, but in the end you want a neat circuit that works properly. And if your circuit does not work properly:!Attempt to reason out the problem. Does the circuit act reliably? !Does it always produce the same wrong result? If so, then the error is likely in the logic.!If it yields different results at different times, a loose connection is very likely. If two output lines are connected together (which should never be done), it can also result in unpredictable outputs.!Test each component of the circuit independently. For example, if you have the expression AB' + ABCD + ABC' built with NAND gates and inverter s, first test that the input and output of (AB')' is working correctly. Then move onto each succeeding term.!Verify the circuit has power and ground to all of the appropriate pins for each chip.!Verify that all of the pins are connected properly. !Make sure that they follow what is specified in your circuit diagrams.!Make sure that none of the output pins are tied together. If each of the output pins were to obtain a different value, this could result in a logic high being tied directly to a logic low level. At best, this can result in an indeterminate value. This will result in further problems if this output is then used as an input for another gate. !Remember that often things do not work the first time when you build them. 24 PAGE 25 This book is licensed under a Creative Commons Attribution 3.0 License DEBUGGING TIP: Do not allow yourself to get frustrated! This is easier said than done, but getting upset does not serve any purpose in effective troubleshooting. If you have done all of the above and things still do not work:!Return to the design phase and verify that your minimization and pinouts are correct.!Sometimes errors come from the components or equipment themselves. Errors such as those listed below can occur, but are very rare. These should be considered as a last resort and other causes of error should be investigated before looking for the following errors:!A pin on a DIP can become bent and curl under the chip so that it does not get inserted into the breadboard This is difficult to see without taking the chip out and examining its legs.!In general, solid state devices are very reliable when operated under proper temperature ranges, but very occasionally a chip may be faulty. !Connecting wires can be split inside of the insulation. When this occurs, the insulation will cause the wire to look as though it is intact, but if the copper is in two pieces inside the insulation, current will not flow and the wire will actually be open.!Faulty test equipment can adversely effect the circuit being tested and lead one to believe a circuit is malfunctioning when it is not, or give you other false information that leads you down the wrong path in your reasoning.!Ask for help from fellow classmates and your instructor.!Take a break and come back to the problem. No one works at their best when they are totally aggravated.Review exercises1. Design a 4input NAND gate using two 2input NAND gate s and one 2input NOR gate. Hint: Use DeMorgan's law. 2. What are the possible groupings in a 4input Kmap ? Sketch their shapes. 3. Construct a truth table for the following functions: (a) f(A,B,C) = AB + A'BC' + AB'C (b) g(A,B,C) = A'C + ABC + AB' (c) h(A,B,C,D) = A'BC' + (A B)C + A'B'CD' + ABC (d) j(A,B,C,D) = A'C'D' + C'D + CD 4. Con stru ct t he Kmap for each of the functions from the previous problem and de termine the minimal expression for each. 5. For 3(b), design the circuit for the minimal SOP expression found in problem 4 using just NAND gates and inverter s. Label the pinouts on the circuit diagram.Introduction to Digital Logic with Laboratory Exercises25 A Global Text PAGE 26 3. Logic simplification 6. For 3(c), de sign the circuit for the minima l SOP expression found in problem 4 using just NAND gates and inverter s. Label the pinouts on the circuit diagram. 7. Given each of the Kmap s, determine the minimal expression associated with it. (a) (b) (c) (d)Procedure1. Write the prelab in your lab notebook for all the circuits required in the steps that follow. 2. Obtain instructor approval for your prelab. 3. Build the circuit required for Exercise 5 from the review exercises. (a) Make sure to test each of the portions of the expression independently. Meaning, te st the outp ut of each of the first level NAND gates to verify that each works before testing the final output. (b) Demonstrate the working circuit for your instructor. 4. Repeat the steps from the last procedure for Exercise 6 of the review exercises. 26 A'0A1B'01 1B11 0 A'B'00A'B01AB11AB'10C'01 1 1 1C10 1 0 0 A'B'00A'B01AB11AB'10C'D'001 1 1 1C'D011 1 1 0CD110 0 1 1CD'100 0 1 1 A'B'00A'B01AB11AB'10C'D'000 0 0 0C'D011 1 0 1CD110 1 0 1CD'101 1 0 0 PAGE 27 This book is licensed under a Creative Commons Attribution 3.0 License 4. More logic simplificationLearning 0bjectives!Review all possible Kmap groupings.!Use don't care conditions in minimization.Additional Kmap groupingsSome of the rectangular groupings allowed for Karnaugh map s, such as the one in Exhibit 4.1 are not obvious. Cells on borders actually ar e a djacent to cells on the opposite border, whi ch produce gr oupings t hat may not appea r continuous. This grouping of two cells actually forms a rectangle represented by B'C', even though this rectangle is split. The possib ilities for nonobvious groups increase for Kmap s with fourinput functions. Exhibit 4.2 shows B'D, a four cell squar e grouping that is split on the two side borders. In Exhibit 4.3 the eigh t cell rectangu lar grouping D' is shown. One of the most nonobvious four cell groupings that contains all four corners is shown in Exhibit 4.4 The intereste d reader can verify that the minim al express ions for Exhibit 4.2 4.3 and 4.4 are B'D+A'D+A'B'C, D'+AB'+A'C' and B'D'+A'BD+A'CD respectfully.Introduction to Digital Logic with Laboratory Exercises27 A Global Text Exhibit 4.1 : Kmap grouping PAGE 28 4. More logic simplification despite t he ordering of the input vari ables. In Exhibit 4. 5 the same function is represente d as in Exhibit 4.3 In this case, the region highlighted for D' does not span two boundaries, while the grouping for A'C' does in this format. Again, it can be shown that the same minimal expression is obtained: D' + A'B + A'C'.Don't care conditionsWhile all input cases for a logical function must be considered, in an actual des ign it often occurs that certain cases never exist. For instance, a particular counter that cycles through the states zero through five would never reach states six (11 0) and seven (111). In such cases, it can be advantageo us to fill the spots for these cases with a don't care condition ( d ). The don't care can then be included with a grouping if it helps to minimize the fin al l ogical representation, otherwi se it can be treated as false. Consider the example in Exhibit 4.6 If only the ones are grouped, the minimal expression is C'D' + A'BC' + BD'. However, if the don't care c onditions are allowed to be grouped with ones, the resulting minimal expression is B + C'D'. Remember that the presence of a don't care condition does not require that this cell be covered in the final o u t p u t Exhibit 4.7 demonstrates this case. Note, two of the don't care s are included to yield a minimal representation of C'. The don't care along the bottom is not included at all. 28 PAGE 29 This book is licensed under a Creative Commons Attribution 3.0 License Review exercises1. Given each of the Kmap s, determine the minimal SOP expression. d represents a don't care condition. (a) (b) (c) (d) (e) (f) 2. For the functions listed below, construct a Kmap and determine the minimal SOP expression. a. f(a,b,c) = a'b'c' + a'bc' + abc' + abc b. g(a,b,c) = ab'c' + abc' + abc + don't care s(a'bc + ab'c) c. k(a,b,c,d) = abc'd + ab'c'd + a'bc'd + a'b'cd' + don't care s(a'b'cd+ a'bcd + ab'cd + abcd) d. m(a,b,c,d) = a'b'cd' + a'bcd' + abc'd' + abcd' + ab'c'd' + ab'cd' + don't care s(a'bc'd + abc'd)Introduction to Digital Logic with Laboratory Exercises29 A Global Text A'B'00A'B01AB11AB'10C'D'000 0 0 1C'D010 0 1 1CD111 0 1 1CD'101 0 0 1 A'B'00A'B01AB11AB'10C'01 1 0 1C10 1 1 0 A'B'00A'B01AB11AB'10C'D'001 1 0 1C'D010 1 0 0CD110 1 0 0CD'101 1 0 1 A'B'00A'B01AB11AB'10C'00 0 1 1C11 d d 1 A'B'00A'B01AB11AB'10C'0d 0 1 1C11 0 0 d A'B'00A'B01AB11AB'10C'D'001 1 0 0C'D011 1 1 1CD110 0 0 0CD'101 1 0 0 PAGE 30 4. More logic simplificationProcedure1. Write the prelab in your lab notebook for all the circuits required in the steps that follow. 2. Obtain instructor approval for your prelab. 3. Build the circuit required for Exercise 2(b) from the review exercises. 4. Demonstrate the working circuit for your instructor. 5. Repeat the steps from the last procedure for Exercise 2(c) from the review exercises. 30 PAGE 31 This book is licensed under a Creative Commons Attribution 3.0 License 5. MultiplexerLearning objective!Use the multiplexer to implement complex logical functions.Background on the muxA multiplexer o ften ju st called a mux, i s a device that c an selec t i ts output from a number of inputs. This de vice is use ful in computer syste ms that use a bus architecture, where several devices share the same communication path. A 2to1 multiplexer i s s hown in Exhibit 5.1 In this case the two inputs are D0 and D1. If the selec t line is low, then the output will reflect the state of D0. Lik ewise, if the sele ct line is high, the outp ut is the state of D1. Hence, the output is switched betwe en t wo d iffere nt devices c onnected t o D0 a nd D1 using t he select line. In this way, only one device will be active or connected to the bus at any given time. Exhibit 5.1: 2to1 multiplexer With an increase in the number of select lines, multiplexer s allow for more than just two input lines. If two select lines a re use d, then the o utp ut c an be s elected f rom f our different inputs forming a 4to1 mux. T he 74151 provide d in your kit i s an 8to1 m ux that u ses t hree s ele ct lines to c hose f rom 8 differe nt i nput lines. A d iagram o f t he 74151 chip is given in Appendi x A. The 8to1 multiplexer c an be used to take a byte o f parallel data on the input lines and det ermine which of the input lines to display at the output. This is useful with bus archite ctures in order to convert the parallel data that most often comes in bytes into a serial stream of bits. Using a multiplexer to implement logical functionsAnother use for the mux is to impleme nt fairly complicate d logic functions without the aid of other logic gates. As an example, examine the following function along with its Kmap and the resulting minimal SOP expression. g(a,b,c) = a'b'c' + a'bc + ab'c' + ab'c + abc' = a'bc + b'c' + ac' + ab' In order to impleme nt the circuit of this function for even the minima l SOP representation, five NAND gates are required. However, a single mux can be used to implement the same express ion. The key is to use the input vari ables for the function as the input for each sele ct line and set the data lines to the value for each of theIntroduction to Digital Logic with Laboratory Exercises31 A Global Text PAGE 32 5. Multiplexer corr espon ding outputs. Not e t hat the v alue of data l ines D 0, D3, D4, D5, and D6, whi ch a lso are f ound on pins 4, 1, 15, 14 and 13 a re set t o h igh with t he remaining d ata lines set low. In this manner, any three input logical functions can be built with a single mux. Note that as mentioned previously, the strobe pin is tie d low and the order of the inputs from the function differ from the order of the input lines for the 74151 chip. A'B'00A'B01AB11AB'10C'01 0 1 1C10 1 0 1Table 15 : g(a,b,c) A B C f 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0Table 16 : g(a,b,c) Exhibit 5.2 : Circuit for g(a,b,c) When used in this manner, the 74151 is often referred to as a boole an function generator. This circuit could be even more flexible if the data input lines, D0 through D7, could be changed. The function that the multiplexer imple mented c ould be changed w hile the circuit i s running w ith the u se of memory c hips t o s tore temporary va lues for the input lines to create a truly programmable boolean function generator. When using the 74151 multiplexer : (1) Make sure to properly select the strobe line. (2) Note that values chosen for A, B, and C may differ from those given in the truth table in Appendix A. Appendix A assumes that C is the most significant input line, which may not be the case in your design. Just as this method of using an 8to1 mux can be used to implement any 3input function with just one chip, any 4input function c an be built with a 16to1 mux. However, the kit provided with this lab only contains the 8to1 mux. This can present a problem when a complex four input function wou ld require several differe nt 7400 serie s 32 PAGE 33 This book is licensed under a Creative Commons Attribution 3.0 License chips to implement, such as the function h(a,b,c,d) found in the Kmap and truth table that follow. Two differ ent minimal SOP expressions exist for this function. h(a,b,c,d) = a'bc' + a'b'c + acd' + ab'c'd + a c'd' h(a,b,c,d) = a'bc' + a'b'c + acd' + ab'c'd + a bd' Either of the terms at the end of each expression could be used to obtain a minimal expression. Yet, either would require four 3input NAND gates, one 4input NAND gate and one 5input NAND gate, assuming that your kit even provided NAND gates with four or five inputs. It may not be obvious how to use the multiplexer in cases such as this to implement the function. One approach would be to use two mux chips along with some additional gates. One trick is to use two 8to1 multiplexer s along with one 2to1 mux as shown in Exhibit 5.1. Each half of the function is implemented with an 8to1 mux and the output of each is selected using the remaining input as the select line for the 2to1 mux. Luckily, a simple trick can be used with an 8to1 mux. First take the function given in the Kmap for h(a,b,c,d) produce the truth table, but add one column for the multiplexer input of each data element. a'b'00a'b01ab11ab'10c'd'001 1 0 0c'd010 1 0 1cd111 0 0 0cd'101 0 1 1Table 17 : h(a,b,c,d) Each of the two rows in the sixth column now represent one of the input lines. In stead of the input lines taking just true or false to impleme nt the truth table directly, the input lines will take the va lue of true, false, d, or d'. In this way, only one multiplexer needs to be used along with pos sibly one inv erter gate. As a, b, and c are used to select the data line, each set of two rows that share the same input va lues for a, b, and c are groupe d toget her in the table. Then by comparing the output v alue o f h for these t wo rows, it can be de termined what value the data line should take. For example, since h matches input d for the first two rows, the input va lue for D0 should be t ied to input d The c ircuit that i mplements h(a,b, c,d) is given in Exhibit 5.3 It is assumed that the inverse of the input d is available somewhere in the circu it, if not, an invert er would need to be added to this circuit. a b c d h(a,b,c,d) Input 0 0 0 0 0 D0=d 0 0 0 1 1 D0=d 0 0 1 0 0 D1=0 0 0 1 1 0 D1=0 0 1 0 0 1 D2=1 0 1 0 1 1 D2=1 0 1 1 0 0 D3=d 0 1 1 1 1 D3=d 1 0 0 0 0 D4=d 1 0 0 1 1 D4=d 1 0 1 0 1 D5=d' 1 0 1 1 0 D5=d' 1 1 0 0 1 D6=1 1 1 0 1 1 D6=1 1 1 1 0 0 D7=0 1 1 1 1 0 D7=0 Table 18 : h(a,b,c,d)Introduction to Digital Logic with Laboratory Exercises33 A Global Text PAGE 34 5. Multiplexer As the mux can implement logical functions directly from the truth table without the need for any logic minimi zation, it is often tempting to use the mux to impleme nt every function and simply skip the minim ization tech niques described earlier. Resist this temp tation! Oft en the minimal SOP impleme ntation will require few gates resulting in a simple des ign without a mux. In addition, when different functions are required for a given circuit, if o n l y multiplexer s were used, a mux would be need ed for each and every function. However, the minimal SOP expres sions for the different functions will somet imes share common logical terms. Examine the two functions below that are required for a given circuit. f(x,y,z) = x'yz g(x,y,z) = z' + x'yz They share the term x'yz, and this part woul d only need to be built once and could be used for both functions, saving gates. Sharing of terms in this manner is not possib le when using the mux to implement functions. So in order to insure that the simplest circuit is designed to im plement the function, the logic minimization techniques described earlier should be examined first before resorting to the mux to implement a function. 34 PAGE 35 This book is licensed under a Creative Commons Attribution 3.0 License Review exercises 1. Construct the truth table and Kmap for each of the followi ng functions and de termine the minimal SOP expression. (a) f1(a,b,c) = a'b'c' + a'bc' + a'bc + ab'c' (b) f2(a,b,c) = a'b'c + a'bc + abc' + ab'c (c) f3(a,b,c,d) = a'b'c'd' + a'bcd + abcd + ab'c'd' + ab'c'd (d) f4(a,b,c,d) =a'b'c'd' + a'bc'd + abcd + a'b'cd' + a'b'cd + a'bcd' + ab'c'd 2. Design the implementation of expression 1(b) using an 8to1 mux. 3. Design the circuit that will implement 1(d) using an 8to1 mux chip along with any necessary circuitry. 4. Examine the following fourinput functions and design a circuit that will implement each. (a) g1(a,b,c,d) = a'b'c'd + abcd + a'bcd + a'bc'd + ab'c'd + a'b'cd + abc'd + ab'cd (b) g2(a,b,c,d) = a'bc'd + a'b'cd' + ab'cd (c) g3(a,b,c,d) = abc'd' + abc'd + abcd + abcd' + a'bc'd + a'bcd (d) g4(a,b,c,d) = a'bc'd' + abc'd' + abcd' + ab'cd' + a'bc'd + abc'd + abcd + ab'cdProcedure1. Write the prelab in your lab notebook for all the circuits required in the steps that follow. 2. Obtain instructor approval for your prelab. 3. Build the circuit required for Exercise 2 from the review exercises of the previous chapter. Demonstrate the working circuit for your instructor. 4. Repeat the steps from the last procedure for Exercise 3 from the review exercises. Introduction to Digital Logic with Laboratory Exercises35 A Global Text PAGE 36 This book is licensed under a Creative Commons Attribution 3.0 License 6. Timer s and clocksLearning objectives!Review relation between time and frequency .!Construct timer and clock circuits.!Produce a timing digram for a circuit.Timing in digital circuitsTiming circuits are often required for various applic ations. One may nee d to measure the length of time that a given switch has been on or off. As will be seen in future labs, for more complicated circuits, a clock is often neces sary t o synchronize the various c omponents. While m any differ ent ways exist to build timing c ircuits, the 555 timer chip has proven to be an industry standard for this purpose. 555 timerT h e 555 timer chip was first manufactured in the early 1970s and continues to be use d in electron ic de vi ces. As can be seen in the de tailed circuit diagram given in Appe ndix A for this integrated circuit, it contains two diodes, many resistor s and over twenty transistor s. All of this i s contained in one smal l dual inline package tha t can be used in timing and clock ing circuits. It is important to note t hat propagation delay s caused by the time it t ak es for signals to travel through the circuit compone nts prevent it from being used in circuits requiring fast swit ching times. In this case, fast is considered a few !se conds. The propag ation dela y varies slightly dep ending upon the version of the 555 being used. This limitation prevents the 555 from reaching spee ds nece ssary for modern computer syste ms. However, many applicat ions have less rigorous requirements for which the 555 timer h as proven to be the component of choice. Due to mass production, this chip is widely available at a modest price.Timer sA timing circuit using the 555 timer is found in Exhibit 6.1 This circuit is also called a oneshot because it will work once for every time it is triggered properly. After being trigger ed, it turns on for the specified time and then returns to its stable state of off. It is also often said to be operating in monostable mode because it only has one stable state, when its output is low, ground or off. The circuit is triggered with a voltage below (1/3)Vcc (Vcc is the supply voltage for the circuit), at which time the capacitor labeled C begins charging through the resistor l abeled R. At the time when the voltage on the capacitor reaches (2/3)Vcc, the outp ut will turn low. The voltage across the capacitor is given belo w. See Append ix B for more information regarding resistor s and capacitors.Introduction to Digital Logic with Laboratory Exercises36 A Global Text Exhibit 6.1 : Timer circuit PAGE 37 6. Timers and clocks V(t) = Vcc( 1 e(t/rc)) Setting V(t) equal to (2/3) V cc and solving for t yields the time when the outp ut will go low (assume three digits of accuracy). t = 1.10(RC) Note that the values for resistor s and capacitors often vary with a tolerance of 5 per cent and 10 per cent respectively. Hence, the time of the timer may not exactly match the calcul ated va lue. When it is critical for the application to have a very spec ific time, either the compone nts use d must be measured to insure that they match the time needed or a variable resistor can be used so that it can be adjusted once the circuit is built. ClocksJust as the drummer in a band he lps to k eep the rest of the members synchronized, so d oes the clock in a circuit. A clock i s used to synchronize a circuit that contains different components that have diff erent propagation de lays. Synchronization is required bec ause signal changes take time to travel through a circuit. Internal inductance and capacitance found in the wires of the circuit and the components themselve s cause de lays. In order to insure that each transition or change has fully propagated through the circuit, the clock can only switch as fast as it takes the slowes t part of the circuit to fully register each change. Modern proces sors ha ve clock s that operate in the gigahertz range and are built with the use of crystals. The 555 timer chip cannot be clock ed that fast due to the internal propagation d elay within the transistor s in the c hip, but it can provide a reliable clock pulse for applications that do not require that speed. Clock speeds are given in te rms of frequency which uses the unit hertz; this stands for cycles per second. So if a clock is said to have a frequency of 20 0 megahe rtz, it t ransitions f rom l ogic high t o logic l ow 200,0 00,0 00 times in one second! Another measure often associated with a clock is its period, which is the time it takes for the full clock cycle. The period of the 200 megahertz clock is 5 nanoseconds. T = 1/ f M a t h e m at i ca l l y period (T) and frequency (f) are relate d inv ersely. The clock waveform given in Exhibit 6.2 illustrate s an ide alized waveform. In realit y the transitions from low to high or high to low take some time and are not instantaneous as those shown. As another example, a 5 gigahe rtz clock has a period of 1/5,000 ,000 000 seconds, which is 0.0000000 002 seconds or 0.2 nanosecond s. The clocks built for these labs will be much slowe r than this. The fastest clock will have a period of one second. 37 PAGE 38 This book is licensed under a Creative Commons Attribution 3.0 License Exhibit 6.3 shows a clock circuit using the 555 timer When configured in this manner, it is said that the timer i s operating in astable mode. This means that there is no stable state for the circuit; it just continues to oscillate, going from low t o high and back again. In this case, the trigger is tie d to the voltage across the capacitor, so that the circuit is trigger ed by itsel f. The capacitor is charged through the series combination of R1 and R2 and discharged t hrough R2. The capacitor charges to 2 /3*Vcc and th en discharges to 1/3*Vcc repeatedly. Using the same method given in the previous section, the times to charge and discharge the capacitor along with the equations for the period and frequency are listed below. t1 = 0.693(R1 + R2)C charge time t2 = 0.693(R2)C discharge time T = t1 + t2 = 0.693(R1 + 2*R2)C period f = 1/T = 1.44/((R1 + 2*R2)C) frequency Note that the accuracy of the values of the resistor s and capacitors will affect the actual va lues for the frequency of t h e clock Also, this clock will not have a symmetric waveform as it will be charging (on) for a longer time than it will be discharging (off). When measuring the frequency of the clock count the time for t en full clock pul ses a nd then divide this number by ten to de termine the period. This will reduce the ef fect of timing errors introduced by those taking the measurements. Timing diagrams The graph of the logical transition for a circuit is given in a timing diagram. Tim ing diagrams provide a visual trace of the circuit functionality. They can also be helpful in determi ning the maximum possib le delay for a given circuit which can then be u sed to d etermine the fastest frequency in which the circuit can be clock ed. The diagrams disp lay each va lue in one of three different states: logic high, logic low, and inde terminate. The indeterminate state wou ld occur when a given state cannot be guaranteed to be eit her high or low. In de te rminate states are usually shown as gray areas that span the entire region from low to high for the duration of the indetermi nate period. The transition ed ges are often not shown to be totally vertical, as they are in Exhibit 6.2 This is to illust rate the point that changes in output are not instantaneous due to de lays caused by transition t imes as well as internal inductance and capacitance in the circuits. The timing diagram shown in Exhibit 6.5 is for the circuit found in Exhibit 6.4 This circuit has three extra points listed: A, B, and C to determine the intermediate states of each of the gates for a given transition. In this case, va lues for D0 is assume d to be logic high and D1 is assume d to be logic low with the SELECT line making a transition from logic low to logic high. A is the output of the inverter B the output of the top AND gate, and C the outp ut o f t he lower AND gate. The c ircuit i s assumed t o b e i n a stable state with the inputs SELECT, D0, and D1 at logic low, high, and low prior to time zero. Assume that the manufacturer specifies that each gate will have aIntroduction to Digital Logic with Laboratory Exercises38 A Global Text Exhibit 6.3: Clock Circuit PAGE 39 6. Timers and clocks maximum delay of 10.0 nanoseconds. This may vary dep ending upon the logic family used, so the data shee t should be consulted for verification when determi ning the maximum de lay for a given c ircuit N otic e t hat o nce the SE LECT line is brought low, A, B, and the Output all assume an intermed iate value as there is no guarantee of how f a s t t h e t r a n s i t i o n w i l l o c c u r O n c e a t 1 0 0 nanosecond s, the output of the inverter can be verified to have gone low and the state for A is listed as low. This transition value then ripples through the other gates as the top AND gate now takes another 10.0 nanoseconds to insure that its output has changed from high to low. Output changes may occur faster than the times liste d, however as that cannot be guarantee d, the slowest time must be used to determine the fastest frequency in which a circuit can be clock ed. If this circuit were to be clock ed, since the maximum dela y for the entire circuit is 30.0 nanoseconds, this wou ld also be the smallest allowable value for the period of the clock which wou ld yie ld a maximum frequency of 33.3 Mhertz. In the se labs, the circuits will be clock ed at a slow enough rate that delay s on the order of nanoseconds will not impact the circuits. However, for circuits where spee d is essenti al, de tailed analysis such as this is critical to insure that the circuit is clock ed as fast as possible while still allowing enough time for the circuit to stabilize.Accuracy of answersAs this chapter involves answers that go beyond the simple binary, true or false format, a brief discussion of the accuracy of the numbers follows. When answers are provided, it is beneficial to know how accurate those answers are. The precision of any measurement is dependent upon the accuracy of the de vice that is used to perform the measurement. For e xample, one wou ld not e xpe ct to obtain measurements within tho usandths of a sec ond u sing an ordinar y wristwatch or within thousandths of a millimeter using a standard ruler. Once the accuracy of the 39 Exhibit 6.4 : 2x1 Multiplexer PAGE 40 This book is licensed under a Creative Commons Attribution 3.0 License measurements used is underst ood, it is important to remember the rules that apply to the number of significant digits for any calculation.!Trailing zeros are significant to the number.!Use all digits when performing calculations and round only for the final answer.!When numbers are multiplied or divided, the final answer has the same number of significant digits as the number with the smallest amount of significant digits in the calculation. In this book, the formulas are provided using three digits of accuracy. It may be the case that fewer digits can be obtained for a given measurement or that the components use d are known to only within one digit of accuracy. In these cases, the final answers should be rounded accordingly. As mentioned, the tolerances of the compone nts will cause de viation of the measured answe r from the theoreti cal answer. The tolerance of the resistor s used in these labs is 5 per cent while the capacitors have a tolerance of 10 per cent. This means that for a 100 0 ohm resistor that resistor i s guaranteed to be between 950 and 1050 ohms. 1000 0.05(1000) < actual value < 1000 + 0.05(1000) Likewise, a 1 mircofarad capacitor is guaranteed to be between 0.9 F and 1.1 F 1 .1(1) < actual value < 1 + .1(1) This may cause the measured answer to diff er quite a bit from the answe r calculate d using the formulas. In addition, when the values of the resistor s and capacitors are multipli ed tog et her, as is the case with the formulas above for the timer and clock these tolerances are compou nde d. For example, assume that a 100,000 ohm resistor is combined with a 100 F capacitor to produce a time of 10.1 seconds. t = 1.10(RC) = 1.10*100,000*0.0001 = 11.0 seconds. However, if we take the worst case for each value, we can see that the answer will actually be within 15%. 1.10(95,000)(0.00009) < actual value < 1.10(105,000)(0.00011) 9.41 < actual value < 12.7 For this reason, it should not be assumed that the final values for the clock and timer will match exactly the values calculate d theo retically. The tolerances of the components use d will often mean that the theoret ical value of the clock or timer may only have one significant digit of accuracy. When the accuracy o f the timer or clock is important, either components must be measured bef ore being used to insure their va lues, components with smaller tolerances should be used (which is more costly), or resistor s with adjustable va lues (potentiometers) can be used and adjusted after the circuits are built. Of course adjusting the potentiometers is time consuming and thus costly.Review exercises1. What is the period in seconds of the clock with the given frequencies? (a)6.00 Ghertz (b)10 Mhertz (c) 6000 RPM ( NOTE: 60 seconds are in each minute) 2. For the given period, determine the frequency of the clock in Hertz.Introduction to Digital Logic with Laboratory Exercises40 A Global Text PAGE 41 6. Timers and clocks (a)10.0 sec (b)0.0500 nanoseconds (c)1.00 milliseconds 3. Assume dela y for each logic gate is 10. 0 nanoseconds for the circuit in Exhibit 3.3 and that input values of A is l ow and B and C are a ll a t logic high. Draw a timing d iagram f or a transition a t time zero that t akes input for C from logic high to logic low. List input A, B, C, and Output as well as values for pins 3, 6, and 10. 4. If the delay for each logic gate is 10.0 nanoseconds, what is the maximum frequency that the circuit from Exhibit 2.14 can be reliably clock ed in order to insure proper operation? 5. A 100 F capacitor is used to build timer s. Three timer s are to be built with times of 1, 5 and 10 seconds. a. What resistor s should be chosen to obtain the times provided? b. Assuming that you are limite d to choosing the values provided in the lab, which resistor s should be chosen to come as close to the desired va lues as possible? Recall that when resistors are added in serie s, the total resistance is the sum of the resistors. c. Draw a schematic of the 5second timer d. G iven that c apacitors h ave a tolerance o f + 10 per cent and resistors have a t olerance o f + 5 p er cent, what range of values could you expect for your timer? 6. A 100 F capacitor is used to build clock s. Two clock s are to be built with periods of 1 and 5 seconds. a. Using va lues of resistor s provided in your lab, pick two resistor s that yield periods as close to those desired as possible. b. What is the time on and time off for each of the clock s during one period? c. Draw a schematic of the 5second clock.Procedure1. Write the prelab in your lab notebook for all the circuits required in the steps that follow. Include all necessary equations and calculations. 2. Obtain instructor approval for your prelab. 3. Build and test the 5second timer from exercise 5. How different is the measured value from the calculated value? Demonstrate the timer for your instructor. 4. Repeat procedure 3 for the 10second timer from exercise 5. 5. Build and test the 1 second clock from exercise 6. a. How different is the measured value from the calculated value? b. Demonstrate the clock for your instructor. 6. Repeat procedure 5 for the 5 second clock from exercise 6. 41 PAGE 42 This book is licensed under a Creative Commons Attribution 3.0 License 7. Memory Learning objectives!Review differences between logic circuits and persistent memory.!Review properties for the SR latch and D flipflop.!Construct a circuit using a flipflop.MemoryYou have often heard the phrase: In order to know where you are going, you need to know where you have been. While all the circuits discussed in previous chapters are very useful, many applications quite simply cannot be implemented without the use of memory to remember where they have been. Modern computer systems employ a w ide array of diff erent memory storage methods that have d ifferent properties. Nonvolatile memory used for secondary storage such as hard drives, CDROM drives, or solid state memory (i.e. an SD card) retains its value after power is shut off. Volatile, dynamic ran dom access memory ( RAM) loses its value when power is shut off and also must have its va lues continually refreshed with external circuitry. Static, volatile ran dom access memory such as that found in cache memory and CPU registers cannot retain its value when power is not provided yet it does not need to be refreshed. This chapter will focus upon the static, volatile, electronic memory listed last. All of the logic circuits built in the previous sections are known as combinatorial logic circuits. They de pend only u pon the state of their inpu ts a t any given t ime and do not take into account a nything tha t has happ ene d in the past. Often it is necessary for the output of a circuit to take past va lues into account. Logical circuits that take past outp ut values a long with p resent i nputs into account t o c ompute the ou tput values a re known as sequential logic circuits. In order to determin e the next state of an outp ut, the previous state must be known. Memory is used to store the history of the state(s) of a digital circuit for use in seque ntial circuits. An example of a sequential logic circuit woul d be a counter. A computer is nothing more than an advanc ed sequential logic c ircuit with memory to store data, programs, and references to the state of programs currently being run.SR latchT w o NOR gates can be configured using feedback to produce one bit of memory. The configuration given in Exhibit 7.1 is known as an SR latch The S, SET and R, RESE T are the inputs and the Q outp ut is provided along with its inver se. The S input is used to set or turn on the latch by setting the outp ut Q high and inv erse low. Similarly, the R input is used to reset or turn off the latch by resetti ng the output to low and the inv erse to high. Once the latch i s set, Q remains a t a logic high w hile both input lines a re off. S imilarly, once the latch i s reset, the Q outp ut will be set to l ogic low and will remain that way whil e both input line s are off. In t his w ay, the latch can store one bit of information indefinitely, or at least as long as it has powe r supplied to it. The NOR SR latch has active high inputs, meaning that if either input is brought high, it will force a corresponding outp ut condition. Note that setting both input values high must be avoided in order to retain the output va lues as oppos ite to each other.Introduction to Digital Logic with Laboratory Exercises42 A Global Text PAGE 43 7. Memory Latches c an also be bui lt u sing NAND gates, bu t t he set a nd reset lines operate in a slightly d ifferent m anner under this configuration. The transitions for these latches are examined in more detail in the exercises. Exhibit 7.1 : SR latch The NAND based SR latch i s an a ctive l ow de vice with a defa ult state of l ogic high f or both S and R inputs. The S and R input values are brought low to change the state. Just as the NOR based SR latch s hould not have both input va lues turned high simultaneously, t he S and R for a NAND b ased SR latch should not be b rought l ow at the same time. S R Q 0 0 state not used 0 1 1 1 0 0 1 1 Q (does not change)Table 20 : NAND SR latchFlipflopsA flipflop is a latch that has bee n modified to work with the use of a clock Clocks are used to synchronize the timing for d ifferent components in a circu it. The output of the flipflop will on ly change when the clock s ignal is in a given state, such as high. Exhibit 7.3 is a D flipflop that will only change when the clock C in the figure, is high. det ermined by the maximum dela y from the gates that are used to construct the device. For this reason, the input to the gate should be stable prior to the clock 43 S R Q 0 0 Q (does not change) 0 1 0 1 0 1 1 1 state not usedTable 19 : NOR SR latch PAGE 44 This book is licensed under a Creative Commons Attribution 3.0 License transition and the time befo re the next clock pulse should last long enough for the output state to stabilize. Manufacture specif ications for the device being used should be consulted to de termine the maximum clock s peed Since these labs only use clock s with periods no faster than 1 second, the circuits designed never approach the limits of the maximum clock spee d. Exhibit 7.4 uses two D flipflops. The output of the first is used as the input of the second creating a masterslave arrangement. This results in a positive edge triggered flipflop. Circuitry can be added to produce JK, T, or D flipflops. The JK flipflop, like the SR latch has two inputs, however all four states are valid for the JK flipflop. Th e T is known as a toggle flipflop be cause if the i nput is hig h, the state of the outp ut toggl es. This means that when clocked with an input of one and a current state of high, the outp ut goes low and if it was low, i t goes high The D flipflop output follows the valu e of the input while e nabled or w h e n clock ed, otherwise it remains in the memory state Both the T and D have only one data input. The table s belo w list the input of the flipflop a long with the present state, Q, and then the next state, QN. The circuit for a r i s in g edge trigger ed D flipflop is provided belo w. JK flipflops are very common in many designs. For the sake of simplicity, only the D flipflop will be used for the designs in this text. Exhibit 7.5 s hows the symbolic represent ation of the D flipflop used for circuit diagram s. The rectangle shown is commonly use d for latch es and flipflops. Also note the bubble in front of the CLEAR line to indicate that theIntroduction to Digital Logic with Laboratory Exercises44 A Global Text J K Q QN0 0 0 0 unchanged 0 0 1 1 unchanged 0 1 0 0 reset 0 1 1 0 reset 1 0 0 1 set 1 0 1 1 set 1 1 0 1 toggle 1 1 1 0 toggleTable 21 : JK flipflop T Q QN0 0 0 unchanged 0 1 1 unchanged 1 0 1 toggle 1 1 0 toggleTable 22 : T flipflop D Q QN0 0 0 off 0 1 0 off 1 0 1 on 1 1 1 onTable 23 : D flipflop PAGE 45 7. Memory 1. Use the SR latch from Exhibit 7.1 Assuming the values in the table represent values that have just occurred, det ermine the stable va lues for the outputs QN and QN'. Recall that the NOR gate is an active high gate meaning any time e ither of t he input va lues is high t he outpu t is low. The first, fourth, and s ixth rows of the table are done for you. The truth table for the NOR is provided. As an example, output for the first row is traced.!S is 0 and Q' is 1, therefore QN stays 0.!R is 0 and QN is 0, therefore QN stays 1.!Stable because Q and Q' retain values. For the fourth row, the outputs toggle.!R is 1, so QN' must be 0.!S is 0 and QN is 0, so QN is 1.!Stable. R is 1, Q is 0 and not affected by Q'. With S and Q 0, Q' stays 1. Tracing the sixth row yields the following.!S is 1, so QN' must be 0.!R is 0 and QN' is 0, so QN is 1. !Stable as S is 1, QN' stays 0. With R and QN' 0, QN stays 1. To start tracing, recall that if any of the input values to a NOR are 1, the output must be 0. 2. Repeat exercise 1 with the latch from Exhibit 7.2 by determining the stable states of all 8 rows of the truth table from the previous problem. While values for QN and QN are provided in rows 1, 4 and 6 for the last problem, you must work all 8 rows for this problem. Remember that the NAND gate has an output of 1 if either of the input values of the gate is 0. 3. Using the D flipflop below, determine the stable outp ut of each of the NAND gates labeled 1 through 4 when the values for D, C, and Q first occur. The following trace for the first row serves as an example. 45 S R Q Q' QNQN'0 0 0 1 0 1 0 0 1 0 ? ? 0 1 0 1 ? ? 0 1 1 0 0 1 1 0 0 1 ? ? 1 0 1 0 1 0 1 1 0 1 ? ? 1 1 1 0 ? ? A BNOR0 0 1 0 1 0 1 0 0 1 1 0 PAGE 46 This book is licensed under a Creative Commons Attribution 3.0 License !Remember the NAND is an active low device, meaning the output will be 1 if either input is 0 (low).! D and C are 0, so NAND1 and NAND2 will be 1. !NAND3 is 0 and NAND2 is 1, making NAND4 1.!NAND1 is 1 and NAND4 is 1, so NAND3 will stay 0.!Stable as neither NAND3 or NAND4 change state. 4. Use the data given for the 74175 in Appendix A to de termine the va lue of the output Q after a rising clock edge has been received by the clock pin. D CLEAR Q 0 0 ? 0 1 ? 1 0 ? 1 1 ?Procedure1. Write the prelab in your lab notebook for all the circuits required in the steps that follow. Include all necessary equations and calculations. 2. Obtain instructor approval for your prelab. 3. Construct an SR latch using NOR gates Verify its operation and demonstrate the circuit for your instructor. 4. Construct one bit of memory using one D flipflop from a 74175 chip. Verify its operation and demonstrate the circuit for your instructor.Introduction to Digital Logic with Laboratory Exercises46 A Global Text D C Q Q' 1 2 3/QN4/QN' 0 0 0 1 1 1 0 1 0 0 1 0 ? ? ? ? 0 1 0 1 ? ? ? ? 0 1 1 0 ? ? ? ? 1 0 0 1 ? ? ? ? 1 0 1 0 ? ? ? ? 1 1 0 1 ? ? ? ? 1 1 1 0 ? ? ? ? PAGE 47 This book is licensed under a Creative Commons Attribution 3.0 License 8. State machinesLearning objectives!Construct state transition diagram s.!Relate the number of memory bits required for a given state machine .!Build four state, state machine s.What is a state machine?A state machine ofte n refe rred to a s a finite state machine i s a sequential logic c ircuit that has a f inite number of def ined states that can be represented. A state machine requires the use of memory to store the state of the machine. Combinatorial logic is used to combine the values of the present state along with inputs to the system to determine the next state of the system. An example of a simple state machine c ould be a counter t hat c ounts from from 0 to 1 t o 2 to 3 and back t o 0. In this case, the state machine does not have any input at all, it uses the past state and increments the value every clock cycle. An example of a complex state machine would be a computer. In this case, the computer can have m any different inputs and has many different states. Input data can come from the keyboard, network, mouse, memory, etc., while the state wou ld normally be associated with the address in memory of the program being run. In this text, the state machine s will be like the counter just described and certainly nothing as complex as a computer. State machines are used in more than just computers. Any process that can be de fined with a given predictable algorithm can often be represente d by an ele ctronic sta te machine. For example, a coff ee vending machine could be automated with a state machine The states wou ld be: waiting for correct change, select options such as cream or sugar, drop cup, dispense coff ee, and dispe nse options. Inputs could include the cream button, sugar button, correct change indicator, and a timer to determine how long to fill the cup with coffee.State transition diagramsA state transition diagram is a graphical representation of the state machine Exhibit 8.1 shows the state transition diagram for a counter that starts at 0 and goe s up through 3 and then back again to 0. This machine has no input, transitioning from one state to the next at every clock pul se. Each state is marked with a circle that contains the va lue of the state. The arrows repres ent the transitions from one state to the next. The state machine shown in Exhibit 8.2.a i s also a four state counter, but it uses one input. The input, labele d x, determin es whe ther the counter continues to increment the count. When x equals 0, the counter counts and when x equals 1, it remains in the current s tate. The convention followed here is as follows: state va lues are listed inside of each state bubble and input values that determine the transition are listed next to each arrow. If the stateIntroduction to Digital Logic with Laboratory Exercises47 A Global Text Exhibit 8.1 : Four state counter PAGE 48 8. State machines will transition regardless of any input, then no input will be liste d nex t t o t hat arr ow. A timing diagram for this four s tate counter is given in Exhibit 8.2.b This assumes that the final c i r c u i t i s clock ed at 1.00 seconds and that rising edge triggered flipflops are use d. N ote that the values of each bit, D1 the most significant bit and D0 the least significant bit, only c hange on the risi ng edge o f th e clock while the input is free to change at any time. This diagram serves a slight ly different purpose than the timing diagram shown in a previous chapter. While the previous diagram was used to det ermine maximum possible delay s for a circuit, this one is used to illustrate the traver sal of the machine through the various states. The timing diagram, like the state diagram can be helpful when attemp ting to verify the operation of a constructed circuit. Exhibit 8.2.a : Four state counter with inputState machine designIn order to design a state machine one woul d need to recognize the inputs of the syst em, the states, and how it transitions from one state to the next. This is graphically represente d with a state transition diagram. Then, the transition diagram should be used to create a truth table that has the inputs to the syst em and current state values as inputs in that table The output of the truth table is the next state of the syst em. Combinatorial logic is used to imple ment the functions required to obtain the next state values for the state machine. All of the Boolean logic minimi zation techniques used in earlier chapters are used at this stage. As memory is used to store the states, the outp ut or next state that results from the truth table is used as the input to the flipflop s toring the state values. 48 PAGE 49 This book is licensed under a Creative Commons Attribution 3.0 License Finally, the flipflops will nee d to be clock ed. In these labs we want to observe the state s, so the clock used has a slow period such as 2 seconds and a frequency of hertz. Example 1: Four state counterThe steps that follow outline the design of a four state counter with no input. The four state counter is relabeled in Exhibit 8.3 to show the values taken for the required two bits of memory label ed Q1 and Q0. The va lues of Q1 and Q0 are given as well, which happen to follow the binary equivalent of the value of the counter. The table below shows how the present state, given by Q1 and Q0, transition at the next clock signal to the next state, given by Q1N and Q0N. Exhibit 8.3: Four state counter with states The next step is to de termine the functions that represent values of the next state, Q1N and Q0N. As the se functions only have two variables, they are fairly easy to de termine without the use of complex boolean algebra or Kmap s. Q0N i s j ust the i nverse of Q0. Q1N i s t he E xclusive OR of the two i nputs. As the l ogic kit d oes not contain a n Exclu sive OR gate, the equivalent logic using AND and OR gates is given along with the equivalent logic using NAND gates only. The resulting circuit is shown in Exhibit 8.4 Q0N(Q1,Q0)= Q0' Q1N(Q1,Q0) = Q1 Q0 = Q1Q0' + Q1'Q0 = ((Q1Q0')'(Q1'Q0)')' Now, in order to create a fully functional circuit, memory needs to be included. In this case, two D flipflops from a 74175 chip will be used. Because the 74175 chip provides the outp ut Q as we ll as its inverse, the design can be simplified by eliminating the inverter s from the diagram in Exhibit 8.4 The full schematic of the circuit is shown in Exhibit 8.5 along with pinout s for each chip. A switch can be used to clock the circuit for test purposes. A clock such as one design ed with a 555 timer from t he previous chapter, should be used in any final design.Introduction to Digital Logic with Laboratory Exercises49 A Global Text Q1Q0Q1NQ0N0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0Table 24 : Truth table PAGE 50 8. State machinesExample 2: Four state counter with input The four state counter given in Exhibit 8.2.a introduces a complexity by adding an external input. The state transition diagram is redrawn in Exhibit 8.6 with the states labeled in binary, Q1 being the most significant bit. The truth table using the three i tems as input: x, Q1 and Q0 and the output given by the next state values Q1N and Q0N is given in Table 25. x Q1Q0Q1NQ0N0 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 0 0 1 0 0 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1Table 25 : Counter truth table The values of the outpu ts for Q1N and Q0N are then listed in Kmap s to determine the minimal SOP expressions. Equivalent expressions using only NAND gates are given. 50 PAGE 51 This book is licensed under a Creative Commons Attribution 3.0 License Q1N = x'Q1'Q0 + xQ1 + Q1Q0' = ((x'Q1'Q0)' (xQ1)' (Q1Q0')' )' Q0N= xQ0 + x'Q0' = ((xQ0)' (x'Q0')')' Exhibit 8.7: Circuit diagram for four state counter with input The logic is then implemented using the 7400 series chips, as shown in Exhibit 8.7 The output of the logic is used to fee d the input of each D flipflop and the output of each flipflop is used as input for the logic. Note that the CLEAR line for the 74175 must be tied to Vcc. The CLEAR line can be used on pow er up to clear or set the flipflop va lue to logic zero. However, if the line is kept low, the va lue of the flipflop will always remain at logic low. The CLEAR can be l eft to float, however this m ak es t he flipflop susceptible to fluctuations in electrical noise. The use ofIntroduction to Digital Logic with Laboratory Exercises51 A Global Text Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'00 1 0 1x10 0 1 1Table 26 : Q1N(x,Q1,Q0) Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'01 0 0 1x10 1 1 0Table 27 : Q0N(x,Q1,Q0) PAGE 52 8. State machines the CLEAR line will be discussed in more detail in the next chapter For now the CLEAR will just be tie d to logic high. For te sting purpos es, a swit ch can be used for the clock However, make sure to read the next sect ion regarding debounced switch es before using a switch for this purpose. Debounced switchesOne word of caution is in order when u sing switches as the clock source. As a switch is a mechanical de vice, they can suffer from bounce. Bounce occurs when the m et al contacts strik e e ach other and bounce before t hey c ome to rest. When this occurs, it can look like the switch changes state multip le times even though it has only gone from open to closed. Switches come in a variety of configurations. Two common versions are the single pole double throw, SPDT or the single pole single throw, SPST shown below. 52 Exhibit 8.8 : SPDT switch Exhibit 8.9 : SPST switch PAGE 53 This book is licensed under a Creative Commons Attribution 3.0 License Review exercises1. How could using a regular switch as the clock source affect the operation of the counter? 2. Draw a timing diagram for the machine that uses the state transition diagram found in Exhibit 8.3 Assume that the machine will u se a clock wi th a period of 1.00 sec onds, that t he flipflops u sed f or t he de sign are rising edge trigger ed and that the machine is in state 01 prior to time zero and that the machine goes through 4 clock pulses. 3. Draw the state diagram for a four state counter with one input where the counter counts up in binary when the input is low and counts in reverse when the input is high. 4. How many D flipflops are required for the counter from problem 3? 5. Determine the logic required for the input of the four state counter from problem 3 and draw a circuit diagram with pinouts. 6. Draw the state diagram for a threestate state machine that counts from 00 01 10 00 etc. as long as the input is low. When the input is high, the counter does not count and stays at its current state. 7. How many D flipflops are necessary for the counter from the previous problem? Are all of the possible states for the flipflops used? If not which ones are not?Procedure1. Write the prelab in your lab notebook for all the circuits required in the steps that follow. Include all necessary equations and calculations. 2. Obtain instructor approval for your prelab. 3. Build and de monstrate the succe ssful operation of the four state counter found in Exhibit 8 .5. Attempt to clock the circuit with both a regular switch and debounced switch Note the difference in performance. 4. Build and de monstrate the succe ssful operation of the two state counter from Exercise 5 of the review exercises.Optional1. Build and de monstrate the succe ssful operation of the four state counter from Exercise 6 of the review exercises.Introduction to Digital Logic with Laboratory Exercises53 A Global Text PAGE 54 This book is licensed under a Creative Commons Attribution 3.0 License 9. More state machinesLearning objectives!Relate number of states to required amount of memory.!Insure state machine s do not enter illegal states.How many bits of memory does a state machine need?The amount of memory or number of flipflops required for a state machine is directly related to the number of states in the state transition diagram The number of possible states that can be represented increases by a power of two f or e ach n ew bit o f me mory a dded. O ne bit of m emory c an represent 21 or two state s, two bits can represent up to 22 or fo ur different s tates, a nd three bits up to 23 or eight diff erent s tates. T o reduce t he complexity of t he design, use the fewe st number of flipflops that would still accomplish the task successfully. If the de sign required a number of states that is not a power of two, then the smalles t number of bits raised to the power of two that is greater than the number of states required should be used. As an example, if three states were required, two bits would be needed, or if six states were required, three bits would be needed. Number of states # 2number of bitsWhat are unused states?A machine that visits the following states in the order listed, 000 0 0 1 011 111 110 100 000, will require three bits of memory. What becomes of the unused states, 01 0 and 101? Several approache s are common when de aling wi th the unused states. Note that any leg al state moves to another legal state, never vi siting the unused states. As the unused state s are never visited, these could be considered as don't care conditions in the Kmap s for the input to the flipflops. This can reduce the complexity of the design. In addition, PRESET and CLEAR lines for flipflops can be used to insure not only that the state machine enters a legal state when powering on, but it also insures that it powers up in a specific initial state. Using PRESET and CLEAR pinsAs the system power s up, logic levels cannot always be guaranteed. What if during this time, the system happened to enter one of the unused states? Depend ing upon the logic that was use d, the system may the n transition into one of the legal states, or it may get stuck indefinitely in one of the ille gal states. In order to guarantee that the system does not enter an illeg al state as the system powers up, the CLEAR lines can be held low temporarily to insure that the memory bits are set to zero or logic low on power up. Exhibit 9.1 has an RC circui t that can be use d to power on to keep the CLEAR line low long enough to insure that the bits are set to zero. When power is first turned on, the capacitor will be uncharged and must charge through the resistor I f th e ti me co nstant, RC, is se t a t s evera l clock cycles, the n the state machine will be guaranteed to start with all ofIntroduction to Digital Logic with Laboratory Exercises54 A Global Text Exhibit 9.1 : RC for Power On PAGE 55 9. More state machines the m emory bits at zero. The 74175 q uad D flipflop i n t he logic kit d oes not off er a PRESET p in. However the same type of RC circuit can be used for other flipflops that do.Assigning unused states to the systemPowering up is not the only time the machine can enter an unused state. At times large transient spikes can occur during storms or when power ing on or off other equipment that can cause logic levels to change unpredic tably. In cases such as this, the machine can still enter a state that was not planned. Even the RC circuit connecte d to CLEAR or PR ESE T pins cannot rescue the state machine in this case. To address this, the designer should add the additional states to the state transition diagram and simply have them transition to a leg al state. In this way, even if for some reason a circuit enters an illegal state, it will quickly shift to one that is allowed. Adding the extra states as well as the RC circuit does inde ed complicate the circuit, however for a final design that will be used in production, it provides assurance that the circuit will perform reliably even when the unexpected occurs.Example 1: Three state counterThe three state counter in Exhibit 9.2 counts up when the input is high and counts down when the input is low. Two flipflop s will be nee ded to implement this ma chine which means t hat four states can be represente d by those two bits. The state 11 is not used in this design. Wha t would happe n if for some reason, the machine would happen to enter the state 11? The effect of entering this unused or illegal state cannot be known until the circuit impleme ntation is finalized. Instead of waiting to see what happe ns afte r the de sign is completed it is best to incorporate this state early on in the design phase. Two approaches will be investigated. The first will shift the state 11 to the legal 00 state on the next clock cycle. The next approach will be to place don't care conditions for the state 11 and then examine the next state that wou ld follow depe nding upon the simplest design that results from using the don't care conditions.Approach 1: 11 00The resu lting state transition diagram a ssuming that state 11 transitions to 00 on the n ext clock cycle is given in Exhibit 9.3 In all of the cases that follow, unused states will be shown as dotted circles in the state transition diagram. Since state 11 will move to state 00 regardless of the input va lue, it is not written on the diagram. From the Kmap s given bel ow, the next state values for Q1 and Q0 are listed as Q1N and Q0N. It is left as an exercise for the reader to det ermine the circuitry r equired to impleme nt this state machine 55 Exhibit 9.2 : 3 state counter Exhibit 9.3: 3 state counter with unused state PAGE 56 This book is licensed under a Creative Commons Attribution 3.0 License Approach 2: Using don't care conditionsThe next approach instead places don't care c onditions for the state 11 as seen in the Kmap s below. By sele cting the minimal expre ssions, the next states for Q1 and Q0 can be found. The resulting expressi ons can be found to be less complex than those from the first approach. The resu lting s tate transition diagram is given in Exhibit 9.4. a Using the don't care c onditions does simplify the l ogic. Notice that the unused state now goes to two different states depending upon the value of the input. The don't care condition labeled as d*, which is x Q1Q0 is grouped with the term x Q1' Q0. This results in a simpler grouping, xQ0, but it does now cause the machine to transition from 11 to 10 when the input x is a logic high. Similarly, the term d** now causes the state 11 to transition to 01. The remaining don't cares are not contained in a group, so the they will transition to 0 at the next state. It is left to the des igner to c are f u ll y e x a m i n e t he r e q u i r e me n t s o f t h e f i n al c i r cu i t t o det ermine if indee d these are don't care conditions. If so, then the transition diagram should be updated to reflect their use in the logic simplification. A s ample timing diagram that starts on the unused s tate 11 and cycles through this new diagram in Exhibit 9 .4.a is given in Exhibit 9.4.b Notice th at the first transition at time 0 is to the state 01. From there the counter counts in reverse as the inp ut i s low transitioning at time 1 to state 00, at time 2 to state 1 0, and th en back to s tate 0 1 a t time 3. Somewhere betwe en t ime 3 and 4 input x goes hig h, but t he st ate does no t change unt il the next rising clock ed ge at time 4. From that point on, with the input high, the counter counts up. This assumes that the circuit will use rising edge triggered flipflops.Introduction to Digital Logic with Laboratory Exercises56 A Global Text Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'01 0 0 0x10 1 0 0Table 28 : Q1N(x,Q1,Q0) = Q1N = x' Q1' Q0' + x Q1' Q0 Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'00 0 0 1x11 0 0 0Table 29 : Q0N(x,Q1,Q0) = x Q1' Q0' + x'Q1Q0' Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'00 0 d** 1x11 0 d 0Table 31 : Q0N(x,Q1,Q0) = x Q1' Q0' + x'Q1 Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'01 0 d 0x10 1 d* 0Table 30 : Q1N(x,Q1,Q0) = x Q1' Q0' + x'Q0 Exhibit 9.4.a : 3 state counter with don't cares PAGE 57 9. More state machinesExample 2: Five state machineThe five state machine shown in Exhibit 9.5 h as two diff erent loops. One of the loops transitions between 000 and 111 while the othe r goes from 00 1 to 010 to 100. This leaves three possible states that are unused. The truth table that follows uses don't care conditions for unused states 011, 10 1, and 1 10 given as d1, d2, and d3 respective ly. The resu lting Kmap s that follow can be used to determine the minimal expressions. If the unused states were to immediatel y go to next state 000, then the minima l expressi ons can be shown as those listed below. It is left as an exercise to draw the new state transition diagram for this design. 57 Exhibit 9.5 : Five state counter PAGE 58 This book is licensed under a Creative Commons Attribution 3.0 License Q2N = x' Q2'Q0' + Q2'Q1Q0' Q1N = x' Q2'Q1'Q0' + xQ2'Q1'Q0Q0N = Q1'Q0' Now, if the don't care c onditions are use d in the des ign for the minimal expressions, the complexity of the results is reduced. Q2N = x' Q2'Q0' + Q2'Q1or x'Q2'Q0' + Q1Q0' Q1N = x' Q2'Q1'Q0' + xQ2'Q0or x'Q2'Q1'Q0' + xQ1'Q0Q0N = Q1'Q0' The resu lts for Q1N Q2 N have two equally minimal forms. The state transition diagram that uses the first minimal form is given in the Exhibit 9.6 Notice that the unused state 011 goes to the legal state 100 if the input is logic high and another unused state, 110 when the input is a logic low. To trace where the external states will go, examine d1 which corresponds to unused state 011. For Q2N, d1 is part of group Q2'Q1 so Q2N will be 1 regardless of the input at the next state. d1 is only grouped if x is 1 for Q1N and not at all in Q0N. It is left t o t he designer of t he machine t o d et ermine if these transitions a re a cceptable given t he s pecifications for the product. Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'Q2' 00 1 0 d1 1x'Q2 01 0 d2 0 d3xQ2 11 0 d2 0 d3xQ2' 10 0 0 d1 1 Table 33 : Q2N Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'Q2' 00 1 0 d1 0x'Q2 01 0 d2 0 d3xQ2 11 0 d2 0 d3xQ2' 10 0 1 d1 0 Table 34 : Q1N Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'Q2' 00 1 0 d1 0x'Q2 01 1 d2 0 d3xQ2 11 1 d2 0 d3xQ2' 10 1 0 d1 0 Table 35: Q0NIntroduction to Digital Logic with Laboratory Exercises58 A Global Text x Q2Q1Q0Q2NQ1NQ0N0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 d1 d1 d1 0 1 0 0 0 0 1 0 1 0 1 d2 d2 d2 0 1 1 0 d3 d3 d3 0 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 1 d1 d1 d1 1 1 0 0 0 0 1 1 1 0 1 d2 d2 d2 1 1 1 0 d3 d3 d3 1 1 1 1 0 0 0Table 32 : Truth table for 5 state machine PAGE 59 9. More state machines It should be noted that all of the de signs shown in this te xt have used only the D flipflop. However, it can often be the case that another typ e can result in a simpler design. JK flipflops can be used to produce ripple counters with minimal extra circuitry. The JK flipflop does have two inputs, so the result ing logic minimization must be done for both the J and the K input, doubling the number of Kmap s required. In order to reduce the required number of parts for the logic kit, only the D flipflop was used. Designers should bec ome familiar using all of the different type s of flipflops so that the y c an be ass ured that they ha ve chosen the one that truly results in a minim al design. Exhibit 9.6 : Five state counter with unused statesReview exercises1. A state machine requires 7 different states. How many flipflops are required for this mach ine? (a) If a machine has no external inputs, what size is the Kmap for one of the required inputs? (b) If the machine has one external output, how large is the Kmap for one of the flipflop inputs? (c) If the design were to use JK instead of D flipflops, how many next state inputs must be determined? 2. Repeat Exercise 1 for a state machine with 14 states. 3. Draw six clock pul ses of the timing diagram for the machine that use s the state transition diagram found i n Exhibit 9.6 Assume that the clock for the machine has a period of 1.00 sec onds, that the machine is in state 011 prior to time zero and that input x is kept at logic high the entire time. 4. A state machine traverses the state s listed in this order 000 001 011 111 110 100 000. There is no external input. (a) Draw the state transition diagram for th is machine. 59 PAGE 60 This book is licensed under a Creative Commons Attribution 3.0 License (b) What are the unused states? (c) Modify the diagram if the unused states transition to 000. (d) Assuming a state machine were to be built using D flipflops, de termine the value of the next state for each of the flipflops. 5. The two bit sequence 00 01 11 10 00 is a Gray code. Gray code s only have one bit change for each transition. (a) Sketch the state transition diagram for the 3 bit Gray code : 0 0 0 001 011 010 110 111 10 1 100 000 ... (b) Assuming a state machine were to be built using D flipflops, de termine the value of the next state for each of the flipflops. 6. A two bit counter is to be built that will count forward, 00 01 10 11 00, when a logical input is set high and counts in reverse order when it is low. (a) Draw the state transition diagram for this state machine (b) Assuming a state machine were to be built using D flipflops, de termine the value of the next state for each of the flipflops. 7. A two bit counter is to be built that will count forward, 00 01 10 11 00, when a logical input is set high and as a Gray code when it is low (00 01 11 10 00). (a) Draw the state transition diagram for this state machine (b) Assuming a state machine were to be built using D flipflops, de termine the value of the next state for each of the flipflops.Procedure1. Write the prelab in your lab notebook for all the circuits required in the steps that follow. Include all necessary equations and calculations. 2. Obtain instructor approval for your prelab. 3. Your instructor will p ick one or more state machines from the various examples from the review exercises for you to build and demonstrate.Introduction to Digital Logic with Laboratory Exercises60 A Global Text PAGE 61 This book is licensed under a Creative Commons Attribution 3.0 License 10. What's next?Hopefully, this introduction has whetted your appetite for this fascinating subject. Modern te chnology simply wou ld not be po ssible without the advan ces and applic ations of thi s s ubject i n t he world in whi ch we li ve. All of the sequential circuits shown in Chapters 8 and 9 are synchronous, meaning the y use a clock. However, sequential circuits designed without clocks, known as asynchronous circuits, can be de signed. As the clock can often insert added delay for the faster components in the circuit, asynchronous circuits can usually be de signed that will respond even faster than synchronous circuits. Timing issues become critical in this case, and the resulting timing analysis can become so complicated that asynchronous circuits are often not chose n over their synchronous counterparts. However, for circuits that require the fastest spee d possible, often asynchronous circuits are considered. In addition, while the circuits design ed in the se labs all use d discret e compone nts, for circuits that are use d in applications tod ay, nearly all o f the comp onents a re fabricated on a single chip. Either Progra mmable Logic Devices (PLDs) can be use d to fit entire state mac hines on a single chip or cus tom chips can be fabricated for a sp ecific t ask. Very largescale i ntegration (VLSI) technique s a re use d to de sign entire s ystem s on a single c hip; a CPU w ith cache memory and a graphics process ing unit would be an example. Comple xities that requir e additional analysis are when the size of the transistors is decreased, speeds of the circuits are increased, and the de sired pow er consumption is lowered. Hardware des cription languages such as Verilog can even be used to synthes ize and tes t circuit performance virtually in software before constructing a single device. Any one of these areas can provide a wealth of challenging proble ms to tackle. It is the hope of this author that the foundation gained from this te xt will prove use ful as you use technol ogy and design applications that require digital logic.Introduction to Digital Logic with Laboratory Exercises61 A Global Text PAGE 62 This book is licensed under a Creative Commons Attribution 3.0 License Appendix A: Chip pinoutsIntroduction to Digital Logic with Laboratory Exercises62 A Global Text PAGE 63 Appendix A: Chip pinouts 63 PAGE 64 This book is licensed under a Creative Commons Attribution 3.0 License Introduction to Digital Logic with Laboratory Exercises64 A Global Text PAGE 65 Appendix A: Chip pinouts 555 TimerA.7 : 555 timer 65 PAGE 66 This book is licensed under a Creative Commons Attribution 3.0 License Appendix B: Resistors and capacitorsResistorsResistors are electronic components that obey Ohm's law: Voltage across a resistor i s equal to the current through the resistor times the resistance of the device. V = I R Resistance is measured in ohms (! ). Current and voltage are relate d by the resistance of the object, if voltage is kept constant and resistance rises, current will fall. L ikewise if resistance decreases, more current will flow, meaning the measure of the current will rise. While many devices have resistance, including the wire used in the se labs, the only resistance that we w ill be concerned with in this manual is the resistance attributed to actual resistor s Man ufac tur ed resistor s come in various forms, however those used here will be standard $ watt resistor s that follow the conventional color code that describes their value. Exhibit B.1 : Sample Resistor E ac h resistor h as four colored st ripes a s shown in the fi gure a bove. Each stripe corr espon ds to a number as shown in Table 36 The formula for the value of each resistor is listed below. Generic Formula: A B x 10C Which for this case yields: 2 0 x 103 or 20,000 %. The first two stripes indicate the numerical value of the resis tance, the third the exponent of ten which will be multiplie d by the numbers from the first two stripes, and the fourth a tolerance of the resistor The diagram above illustrate s how the first three stripe s are used to calculat e the value of the resistor as we ll as the diagr am bel ow. The mnemonic is often sugge sted as a means of remembering the color code. The tolerances will not be utilized in thisIntroduction to Digital Logic with Laboratory Exercises66 A Global Text COLOR VALUE MNEMONIC Black 0 B etter Brown 1 B e Red 2 R ight Orange 3 O r Yellow 4 Your Green 5 G reat Blue 6 B ig Violet 7 Venture Gray 8 G oes White 9 W estTable 36 : Color Codes PAGE 67 Appendix B: Resistors and capacitors lab manual. Another example i s provided in Exhibit B.2 Applying the formula to obtain the value for this resistor is left as an exercise for the reader. Exhibit B.2 : 100,000 Ohm ResistorCapacitorsIn direct current circuits, capacitors can be thought of as charge storage device s. Electrolytic capacitors will be used in these labs. Elect rolytic capacitors appear to look like a tiny aluminum can with two wires. Be cautious when connecting the electrolytic capacitors as they have a polari ty. Insure that the negative terminal of the capacitor is connecte d properly or the capacitor can malfunction and in some cases explod e! The unit of measurement for capacitors is the Farad. Capacitors with higher Farad measureme nts can store more ch arge at a given voltage. 67 Exhibit B.3 : Capacitors PAGE 68 This book is licensed under a Creative Commons Attribution 3.0 License Appendix C: Lab notebookThe lab notebook s hould be a bound noteboo k, m uch l ike a s tandard c omposition notebook The lab not ebook i s used to docu ment the experiment or lab proced ure. Notebooks can serve many purposes: for the author to review the material, for someone els e to replic ate the procedure, or even as a legal documen t for use in patent or court proceedings. The notebook for the se exper iments will be informal, in that the student will hand write all of the content in the notebo ok. Do not misinte rpret the meaning of informal, because the work should still be neat, legible, we ll organized, and complete. Wha t follows are some guidelines that should be used to document the labs from this text. Of course your instructor may add or delete from this list. The lab notebook should:!be bound!have two to three pages at the front dedicated to a table of contents!have numbered pages to use in the table of contents (you may number them yourself) Each lab should contain:!name of lab!your name!partner(s) name(s)!date!brief objective of lab (no more than two sentences)!equipment list required!prelab including:!any necessary diagrams!any necessary equations and calculations!approval of instructor before you begin the lab exercise!results and observations!conclusion Make sure that you:!Do not erase any items. Cross them out and redo the work.!Write only on the right side of each page. This leaves you room to include any corrections.Introduction to Digital Logic with Laboratory Exercises68 A Global Text PAGE 69 Appendix C: Lab notebook While following these guideline s certainly makes it easier for your instructor to review your work, that is not its main purpose. Keep in mind, someone should be able to understand what you did and even replicate your work given your lab notebook. Your lab notebook can be a helpf ul documen t for you. In industry, it can also be a helpful document for others. 69 PAGE 70 This book is licensed under a Creative Commons Attribution 3.0 License Appendix D: Boolean algebraCommutative law: x + y = y + x xy = yx Associative law: x + (y + z) = (x + y) + z x(yz) = (xy)z Distributive law: x(y + z) = xy + xz x + (yz) = (x + y)(x + z) Absorption: x + (xy) = x x(x + y) = x De Morgan's law: (x + y)' = x'y' (xy)' = x' + y' Other laws and properties: (x')' = x x + 1 = 1 (x)0 = 0 x + 0 = x (x)1 = x x + x' = 1 (x)x' = 0 (x)x = x x + x = xIntroduction to Digital Logic with Laboratory Exercises70 A Global Text PAGE 71 This book is licensed under a Creative Commons Attribution 3.0 License Appendix E: Equipment list Quantity Item Description 1 Digital Trainer See detailed description below. 2 pn2222 transistor s Other general purpose npn transistor s may be substituted. 2 1K% 1/4 watt resistor s 2 33K % 1/4 watt resistor s 2 4.7K % 1/4 watt resistor s 2 100K % 1/4 watt resistor s 4 7400 Quad 2 input NAND see note regarding 7400 series chips 4 7402 Quad 2 input NOR 2 7404 6 inverter s 3 7410 3, 3 input NAND 3 74151 8 input multiplexer 2 74175 Quad D flipflop with CLEAR 2 555 timer 1 100 F arad capacitor 1 0.01 F arad capacitorDigital trainerA digital trainer is a single purpose unit that contains several fe atures that facilitate the constru ction and te sting of digital circuits. Digital trainers can be constructe d, but can be found as a unit for a reasonable price. A digital trainer should include:!A breadboard!A 5V power supply which regulates within .25V of 5V!8 LEDs that are wired to turn on with logic 1 and off with logic 0!6 SPDT switches that are wired to logic high (5V) or logic low (0V)!2 SPDT debounced switch es (co nsult Exhibit 8.10 if constructing a digital trainer)Introduction to Digital Logic with Laboratory Exercises71 A Global Text PAGE 72 Appendix E: Equipment list7400 series familiesSeveral of the 7400 series f amilies are acceptable for use with thes e labs. The LS (Low Powered Schottky), ALS (Advanced Low Powe red Schottky) or HC (High speed CMOS) are all widely available, relati vely inexpensive and will all perform acceptably. 72 PAGE 73 This book is licensed under a Creative Commons Attribution 3.0 License Appendix F: Solutions Chapter 1 review exercises1. Exhibit 1.3 contains the diagram illustrating the commonly connected pins on the breadboard. 2. x x! 0 1 1 0 3. Resistor color codes are explained in detail in Appendix B. (a) (b) (c)Introduction to Digital Logic with Laboratory Exercises73 A Global Text PAGE 74 Appendix F: Solutions (d) 4. The ground symbol is given below. 5. The NAND is the opposite of the AND gate. The function has two diff erent variables, each with two distinct answers (T1 or F0), so there should be four (22) different possibilities for the function. A B (AB)' 0 0 1 0 1 1 1 0 1 1 1 06. A B (A+B)' 0 0 1 0 1 0 1 0 0 1 1 074 PAGE 75 This book is licensed under a Creative Commons Attribution 3.0 License Chapter 2 review exercises1. A logic function with three inputs has eight rows because each of the three inputs has two possibilities (number of possible outcomes for each input)(number of inputs) = 232. A function with five inputs will have 25 or 32 different rows. 3. Truth tables follow. It is often easier to obtain the final result if some of the intermed iate va lues that might be nec essary a re obtained first. F or example, i n 3 a. t he t hird c olumn i s AB, the f ourth (AB)' and the f ifth i s B'. These are then used to obtain the final result. (a) y(A,B) = (AB)' + B' A B AB (AB)' B' y 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 1 0 0 0 (b) y(A,B,C) = (A+B)'C A B C A+B (A+B)' y 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 0 (c) y(A,B,C) = (AC)' + (BC) A B C (AC)' BC y 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1 1 1 1 0 1 1 It may not always be necessary to write every intermediate ste p. In this case, (AC)' is written directly instead of first writing (AC) and then t he inverse. If you f ind this c onfusing, make sure not to ski p steps like this. Note t hat many different f unctions can yie ld the sam e result. For example, (AB'C)' is equivalent t o the function above.Introduction to Digital Logic with Laboratory Exercises75 A Global Text PAGE 76 Appendix F: Solutions (d) y(A,B,C) = (A !B)C' A B C A!B C' y 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 0 0(e) y(A,B) = A' + B A B A' y 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 1(f) y(A,B,C) = ((A+B)'(B+C)')' A B C A+B B+C (A+B)' (B+C)' (A+B)'(B+C)' y0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 1 0 1 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 0 0 0 1Another example of a logic function with a different equivalent, (A + B + C). 76 PAGE 77 This book is licensed under a Creative Commons Attribution 3.0 License 4. Solution with pinout below. 5. Solution with pinout below. It is optional to label Vcc and Gnd on the diagram. Most often for a chip, the Vcc is the upp er most right pin and the Gnd is the bottom left, however the chip pinout should always be consulted. Introduction to Digital Logic with Laboratory Exercises77 A Global Text PAGE 78 Appendix F: Solutions Chapter 3 review exercises1. ( (AB)' + (CD)' ) (AB)'' (CD)'' (AB)(CD) ABCD Original Circuit De Morgan's law Double negatives cancel Parenthesis not necessary 2. Singletons have only one elemen t. Doubles are 2x1 rectangles. Groups of four take two forms, a 4x1 rectangle or a 2x2 square. Finally groups of eight take the form of 4x2 rectangles. Rectangles and squar es can be split across borders; further illust rations of this can be found in the next chapter. Example groupings are shown below. A'B'00A'B01AB11AB'10C'D'000 0 0 0 C'D010 0 0 1 CD110 1 0 0 CD'10 1 0 0 0 Three single groups A'B'00A'B01AB11AB'10C'D'000 0 0 0 C'D010 0 1 1 CD111 0 0 0 CD'10 1 0 0 0 Two 2x1 double groupings A'B'00A'B01AB11AB'10C'D'001 0 1 1 C'D011 0 1 1 CD111 0 0 0 CD'10 1 0 0 0 Two groupings of four A'B'00A'B01AB11AB'10C'D'001 0 0 1 C'D011 0 0 1 CD110 0 0 0 CD'10 0 0 0 0 Group spanning boundary A'B'00A'B01AB11AB'10C'D'001 0 0 1 C'D010 0 0 0 CD110 0 0 0 CD'10 1 0 0 1 Four corner group A'B'00A'B01AB11AB'10C'D'001 1 1 1 C'D011 1 1 1 CD110 0 0 0 CD'10 0 0 0 0 Group of eight 78 PAGE 79 This book is licensed under a Creative Commons Attribution 3.0 License 3. Truth tables follow. (a) f(A,B,C) = AB + A'BC' + AB'C A B C AB A'BC' AB'C f 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 1 0 0 1 (b) g(A,B,C) = A'C + ABC + AB' A B C A'C ABC AB' g 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 1 0 1 c) h(A,B,C,D) = A'BC' + (A B)C + A'B'C'D + ABCD A B C D A'BC' (A !B) (A !B)C A'B'C'D ABCD h 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1Introduction to Digital Logic with Laboratory Exercises79 A Global Text PAGE 80 Appendix F: Solutions d) j(A,B,C,D) = A'C'D' + C'D + CD A B C D A'C'D' C' D CD j 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 4. Minimal expressions given for each map. Notice that quite often, the terms in the original are not found at all in the minimal SOP (Sum Of Products) expression. (a) Original expression: f(A,B,C) = AB + A'BC' + AB'C Minimal expression: f(A,B,C) = BC' + AC (b) Original Expression: g(A,B,C) = A'C + ABC + AB' Minimal Expression: g(A,B,C) = AB' + C 80 PAGE 81 This book is licensed under a Creative Commons Attribution 3.0 License (c) Original Expression: h(A,B,C,D) = A'BC' + (A B)C + A'B'C'D + ABCD Minimal Expression: h(A,B,C,D) = A'B + A'C'D + BCD + AB'C Minimal Expression: h(A,B,C,D) = A'B + A'C'D + ACD + AB'C More than one minimal expression exists. In these cases, more than one correct answer exists. (d) Original Expression: j(A,B,C,D) = A'C'D' + C'D + CD Minimal Expression: j(A,B,C,D) = D + A'C' 5. g(A,B,C) = AB' + C This circuit was de signed using only NAND g a t e s T h i s a l l o w s t h e c i r c u i t t o b e imple mented with just one chip. DeMogran's law was used to av oid needing a NOR gate. In addition, an inverter was avoided by using the remaining NAND gate left on the chip to invert input A.Introduction to Digital Logic with Laboratory Exercises81 A Global Text PAGE 82 Appendix F: Solutions 6. h(A,B,C,D) = A'B + A'C'D + BCD + AB'C 7. As the l ogic kit does no t contain a four inpu t NAND gate, comb inations of three and two input NA NDs a re used. The following justification shows that this is indeed a correct implementation. 8. (a) Minimal Expression: A' + B' (b) Minimal Expression: C' + A'B [ (A'B)' (A'C'D)' ]' [ (BCD)' (AB'C)' ]' )' Direct implementation from circuit [ (A'B)' (A'C'D)' ]' '' + [ (BCD)' (AB'C)' ]' '' De Morgan's law [ (A'B)' (A'C'D)' ]' + [ (BCD)' (AB'C)' ]' Double negatives cancel [ (A'B)'' +(A'C'D)''] + [ (BCD)'' + (AB'C)'' ] De Morgan's law A'B + A'C'D + BCD + AB'C' Double Negatives (c) Two different minimal expressions exist for this problem. Minimal Expression: Minimal Expression: C'D' + A'C' + BC' + AC C'D' + A'C' + AB + AC 82 PAGE 83 This book is licensed under a Creative Commons Attribution 3.0 License (d) Three different minimal expressions exist for this problem. Minimal Expression: Minimal Expression: A'C'D + A'BD + A'CD' + AB'D B'C'D + A'BD + A'CD' + AB'D Minimal Expression: A'C'D + A'BC + A'CD' + AB'DIntroduction to Digital Logic with Laboratory Exercises83 A Global Text PAGE 84 Appendix F: Solutions Chapter 4 review exercises1. (a) Minimal Expression: B' + AC' (b) Minimal Expression: A + C (c) Notice that this solution has one of the groupings that spans the boundaries (B'C). Minimal Expression: AB'+ AD + B'C (d) This expression includes the four corner grouping (B'D'). Minimal Expression: B'D' + A'B 84 PAGE 85 This book is licensed under a Creative Commons Attribution 3.0 License (e) Two different minimal expressions exist for this problem. Minimal Expression: Minimal Expression: B'C' + A'C' + BC B'C' + A'B + BC (f) Minimal Expression: C'D + A'D' 2. (a) Minimal Expression: AB + A'C' (b) Notice that not all don't care conditions need to be covered. Minimal Expression: A Introduction to Digital Logic with Laboratory Exercises85 A Global Text PAGE 86 Appendix F: Solutions (c) Minimal Expression: BD + AD + A'B'C (d) Minimal Expression: CD' + AD' 86 PAGE 87 This book is licensed under a Creative Commons Attribution 3.0 License Chapter 5 review exercises1. (a) f1(a,b,c) = a'b'c' + a'bc' + a'bc + ab'c' Minimal Expression: f1(a,b,c) = a'b + b'c' a b c f1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0(b) f2(a,b,c) = a'b'c + a'bc + abc' + ab'c Minimal Expression: f2(a,b,c) = a'c + b'c +abc' a b c f1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0(c) f3(a,b,c,d) = a'b'c'd' + a'bcd + abcd + ab'c'd' + ab'c'd Minimal Expression: f3(a,b,c,d) = b'c'd' + ab'c' + bcdIntroduction to Digital Logic with Laboratory Exercises87 A Global Text a b c d f3 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 PAGE 88 Appendix F: Solutions (d) f4(a,b,c,d) = a'b'c'd' + a'bc'd + abcd + a'b'cd' + a'b'cd + a'bcd' + ab'c'd Minimal Expression: f4(a,b,c,d) = a'b'c + a'cd' + a'b'd' + abcd + a'bc'd + ab'c'd The truth table also shows the inputs required for the multipl exe r which will be used later when implementing the function with a mux. a b c d f4 Mux In 0 0 0 0 1 d' 0 0 0 1 0 d' 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0 d 0 1 0 1 1 d 0 1 1 0 1 d' 0 1 1 1 0 d' 1 0 0 0 0 d 1 0 0 1 1 d 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 d 1 1 1 1 1 d 2. f2(a,b,c) = a'b'c + a'bc + abc' + ab'c 3. f4(a,b,c,d) = a'b'c'd' + a'bc'd + abcd + a'b'cd' + a'b'cd + a'bcd' + ab'c'd Examine truth table from previous problem to understand why input values are chosen. 88 PAGE 89 This book is licensed under a Creative Commons Attribution 3.0 License 4. (a) g1(a,b,c,d) = a'b'c'd + abcd + a'bcd + a'bc'd + ab'c'd + a'b'cd + abc'd + ab'cd Minimal Expression: g1(a,b,c,d) = d When the Kmap is filled out, it can be seen that the minimal solution is simply d. No log ic is need ed a t all! Hopefully, you did not try to write the truth table and implement it with a multiplexer. This illustrates why even though a multiplexer can implement any circuit, the logic should be analyzed first.Introduction to Digital Logic with Laboratory Exercises89 A Global Text a'b' 00 a'b 01 ab 11 ab' 10c'd'000 0 0 0 c'd011 1 1 1 cd111 1 1 1 cd'10 0 0 0 0 PAGE 90 Appendix F: Solutions (b) g2(a,b,c,d) = a'bc'd + a'b'cd' + ab'cd For this problem, first the Kmap shows that this is the minimal expre ssion. Then the truth table is constructed to determine the input values for an 8to1 mux implementation. a'b'00a'b01ab11ab'10c'd'000 0 0 0 c'd010 1 0 0 cd110 0 0 1 cd'10 1 0 0 0 a b c d g2 Mux Input 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 d' 0 0 1 1 0 d' 0 1 0 0 0 d 0 1 0 1 1 d 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 d 1 0 1 1 1 d 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 0(c) g3(a,b,c,d) = abc'd' + abc'd + abcd + abcd' + a'bc'd + a'bcd Minimal Expression: ab + bd The minima l expression is the column ab and the middle squar e bd. This can be implemente d with a single 7400 chip with one NAND gate left over. 90 PAGE 91 This book is licensed under a Creative Commons Attribution 3.0 License (d) g4(a,b,c,d) = a'bc'd' + abc'd' + abcd' + ab'cd' + a'bc'd + abc'd + abcd + ab'cd Minimal Expression: bc' + acIntroduction to Digital Logic with Laboratory Exercises91 A Global Text PAGE 92 Appendix F: Solutions Chapter 6 review exercises1. (a) T = 1/ f T = 1/(6,000,000) = 0.000000167 sec or 167 nsec (b) T = 1/(10,000,000) = 0.0000001 sec or 100 nsec (c) f = 6000 cycles/min 1min/60sec = 100 Hz T = 1/100 = 0.01 sec or 10.0 msec 2. (a) f = 1/T f = 1/(.00001) = 100 Khz (b) f = 1/(0.00000000005) = 20.0 GHz (c) f = 1/(.001) = 1000 Hz 3. Notice that Pin 3 never changes, although the state for Pin 6 and Pin 10 (the output) are i nde te rminate until it can be verified that the logic has successfully traveled through the required logic gates. 4. The logic circuit from Exhibit 2.14 has eigh t logic gates. Many of these gates are in parallel, such as the first two inverters or the two NAND chips from IC1 The longest path for the logic to travel is what determines the maximum frequency that the clock can be traveled. So the longest delay is: (10nsec 5) = 50 nsec f = 1/T = 1/(0.00000005) = 20.0 MHz 92 PAGE 93 This book is licensed under a Creative Commons Attribution 3.0 License 5. (a) Recall that the timer has a delay of: t = 1.10(RC) Solving for R yields: R = t/(1.10C) The required values for R are found in the table, along with those that are easiest to obtain using the resistors from the lab kit. (b) The first R is obtained by putting two of the 4.7 K resistors in series. The second is by putting two 4.7K resistors in series with a 33K resistor. (c) The schematic should look identical to Exhibit 6.1 with the appropriate values for R and C. (d) Lastly, for the values chosen, the span for the times is calculated below. 1 second timer : 1.10(0.95 9400)(0.9 100u) < actual < 1.10(1.05 9400)(1.1 100u) .89 < actual value < 1.2 5 second timer : 1.10(0.95 42400)(0.9 100u) < actual < 1.10(1.05 42400)(1.1 100u) 4.0 < actual value < 5.4 10 second timer : 1.10(0.95 100000)(0.9 100u) < actual < 1.10(1.05 100000)(1.1 100u) 9.4 < actual value < 13 6. Recall that the period of the clock is given by: T = t1 + t2 = time on + time off = 0.693(R1 + R2)C + 0.693(R2)C = 0.693(R1 + 2*R2)C (a) If R1 and R2 are both 4.7K resistors for the first clock and R1 is 4.7K and R2 is 33K for the second, the resulting times are: T(1sec) = 0.693(4700 + 4700)0.0001 + .693(4700)0.0001 = 0.651 + 0.326 = .98 seconds T(5sec) = 0.693(33000 + 4700)0.0001 + .693(33000)0.0001 = 2.61 + 2.29 = 4.9 secondsIntroduction to Digital Logic with Laboratory Exercises93 A Global Text t desired R desired R for lab t actual 1.0 sec 9100 9400 1.0 sec 5.0 sec 45000 42400 4.7 sec 10. sec 91000 100000 11 sec PAGE 94 Appendix F: Solutions (b) Time on for the 1 second clock is 0.65 seconds and off is 0.33, while time on for the 5 second clock is 2.6 seconds and off is 2.3 seconds. (c) The schematic will look exactly like Exhibit 6.3 with the appropriate R and C values inserted. 94 PAGE 95 This book is licensed under a Creative Commons Attribution 3.0 License Chapter 7 review exercises1. Recall, i f either of the input values are 1, the outpu t of t he gate is 0. While the output values of Q and Q' may change, the input values of S and R will not for this table. So, for any row that has S set to 1 the corresponding value for QN' must be 0 and likewise if R is 1, QN must be 0. Using this, some values can immediately be determined with this information. As the output va lues may change, the remaining next state values requir e more examination. S R Q Q' QNQN' 0 0 0 1 ? ? 0 0 1 0 ? ? 0 1 0 1 0 ? 0 1 1 0 0 ? 1 0 0 1 ? 0 1 0 1 0 ? 0 1 1 0 1 0 0 1 1 1 0 0 0 Row 1: Q' is 1, causing Q to be 0 leaving Q' 1. Row2: Q is 1, causing Q' to be 0 leaving Q 1. For rows 1 and 2, the state of Q and Q' does not change. Row 3 & 4 : QN and S are 0, causing QN to be 1. QN at 1 means QN is 0. For rows 3 and 4, the latch is reset. Row 5 & 6: QN and R are 0, causing QN to be 1. QN at 1 m eans QN' is 0. For rows 5 and 6, the latch is set. Row 7 & 8: QN and QN' are not inverse values of each other, which explains why these states are not used for the latch. Final stable values are provided in the second truth table. S R Q Q' QNQN'0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 1 0 0 0 2. For the SR l atch c onstructed with NAND gates, recall that the NAND gate will have an outp ut of 1 if either of the input va lues is 0. In this manner, some of the next state values may be determined immediately. Now, the remaining undetermined rows are examined. S R Q Q' QNQN' 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 1 1 ? 0 1 1 0 1 ? 1 0 0 1 ? 1 1 0 1 0 ? 1 1 1 0 1 ? ? 1 1 1 0 ? ?Introduction to Digital Logic with Laboratory Exercises95 A Global Text PAGE 96 Appendix F: Solutions Rows 1 & 2 : Both QN and QN are 1, not inverses of one another. These states are not used. Rows 3 & 4 : QN is 1 and R is 1, so QN will be 0. These are the set states. Rows 5 & 6 : QN is 1 and S is 1, so QN will be 0. These are the reset states. Row 7 : S and Q' are 1, so QN will stay 0. QN is 0 and R is 1, so QN stays 1. Row 8 : R and Q are 1, so QN will stay 0. QN is 0 and S is 1, so QN stays 1. Rows 7 and 8 are t stable states where the output values do not change. Final values are provided in the second truth table. S R Q Q' QNQN' 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 0 1 0 1 1 0 1 0 0 1 1 1 0 1 ? ? 1 1 1 0 ? ? 3. As t he NAND gate i s an active low gate meaning i f e ither input is 0, the outp ut will go high, some of the values of the table can be determined immediately (these are bolded). NAND1 can be determined by D and C (italic). Where the values of NAND1 and C are known, the value of NAND2 can be determined (highlighted in yellow). Where NAND1 or NAND2 are known to be 0, the corr espon ding gates NAND3 and NAND4 must be 1 (shown in light blue). D C Q Q' 1 2 3/QN4/QN' 0 0 0 1 1 1 ? ? 0 0 1 0 1 1 ? ? 0 1 0 1 1 0 ? 1 0 1 1 0 1 0 ? 1 1 0 0 1 1 1 ? ? 1 0 1 0 1 1 ? ? 1 1 0 1 0 1 1 ? 1 1 1 0 0 1 1 ? Now treat NAND1 as the S input and NAND2 as the R input to the NAND SR latch (NAND3 and NAND4) and use the work from the previous problem. Rows 1 & 5 : Similar to row 7 from problem 2. Rows 2 & 6: Similar to row 8 from problem 2. The states for Rows 1, 2, 5 and 6 do not change. Row 3 : Similar to row 5 from problem 2. Row4 : Similar to row 6 from problem 2. Rows 3 and 4 correspond to the reset state. Row 7 : Similar to row 3 from problem 2. Row 8 : Similar to row 4 from problem 2. Rows 7 and 8 correspond to the set state. D C Q Q' 1 2 3/QN4/QN' 0 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 0 1 1 0 1 0 1 1 0 1 1 1 0 0 1 1 0 Note than when C is low, the state of the flipflop can never change. Also, due to the addition of NAND1 and 96 PAGE 97 This book is licensed under a Creative Commons Attribution 3.0 License NAND2, the re is never a time when the inputs reach a state that should not be used, as with the SR latches that must avo id certain state s. So when C is low, the s tate remains constant and when C is high, t he state tracks t he D input. The final values are given in the second truth table. 4. When the clear line is low, the value of Q will be low regardless of the state o f D. W hen the value of Clear is high, the va lue of Q wil l be e qual to the value of D at the time of the rising clock edge.Introduction to Digital Logic with Laboratory Exercises97 A Global Text D CLEAR Q 0 0 0 0 1 0 1 0 0 1 1 1 PAGE 98 Appendix F: Solutions Chapter 8 review exercises1. Because switche s suffer from bounce, the circuit could interpret the bounces as clock pulses as well. This would mean that the circuit might be clocked more than once for a given flip of the switch. 2. 3. 4. Two flipflops are needed to represent all four possible states. 5. Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'00 1 0 1x11 0 1 0Q1N( x ,Q1,Q0) Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'01 0 0 1 x11 0 0 1Q0N( x,Q1,Q0) = Q0' 98 PAGE 99 This book is licensed under a Creative Commons Attribution 3.0 License The minima l expression for Q1N i s xQ1'Q0' + x'Q1'Q0 + xQ1Q0 + x'Q1Q0 which is not very minim al. For this reason, the design that follows uses a multiple xer to implement the input for the sec ond flipflop. The first flipflop requires a value that can be taken directly off of the flipflop itself Q0'. Remember to be careful when using the mux, and insure that the Select C line is the most significant bit for the logical expression. 6. Introduction to Digital Logic with Laboratory Exercises99 A Global Text PAGE 100 Appendix F: Solutions 7. The state machine has 3 states so it requires 2 flipflops. 21 < 3 <= 22The state 11 is not used. The next chapter will discuss the design of systems with unused states. 100 PAGE 101 This book is licensed under a Creative Commons Attribution 3.0 License Chapter 9 review exercises1. (a) A state machine that has 7 states will require 3 flipflops. 22 < 7 <= 23(b) With no external inputs, only the existing states provide input to determine the next state, so the Kmaps will be a 4x2 rectangle. (c) With one external input, there will be 4 total inputs, so the Kmaps will be 4x4 squares. 2. (a) A state machine that has 14 states will require 4 flipflops. 23 < 14 <= 24(b) With no external inputs, only the existing states provide input to determine the next state, so the Kmaps will be a 4x4 rectangle. (c) With one external input, there will be 5 total inputs. The Kmaps will be 8x4 rectangles, which are often unwieldy. In this case, alternate minimization techniques should be explored. 3. 4. (a) Introduction to Digital Logic with Laboratory Exercises101 A Global Text PAGE 102 Appendix F: Solutions (b) Of the 8 possible states, 101 and 100 are not represented. (c) (d) Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'00 0 1 0 Q2 10 0 1 1 Q2N( Q2,Q1,Q0) = Q1Q0 + Q2Q1 Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'00 1 1 0 Q2 10 0 1 0 Q1N( Q2,Q1,Q0) = Q1Q0 + Q2'Q0 Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'01 1 1 0 Q210 0 0 0 Q0N( Q2, Q1,Q0) = Q2'Q1' + Q2'Q05. (a) 102 PAGE 103 This book is licensed under a Creative Commons Attribution 3.0 License (b) Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'00 0 0 1 Q2 10 1 1 1 Q2N( Q2,Q1,Q0) = Q1Q0' + Q2Q0 Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'00 1 1 1 Q2 10 0 0 1 Q1N( Q2,Q1,Q0) = Q1Q0' + Q2'Q0 Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'01 1 0 0 Q2 10 0 1 1 Q0N( Q2, Q1,Q0) = Q2'Q1' + Q2Q16. (a) (b) Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'01 0 1 0x10 1 0 1Q1N(x, Q1, Q0) = x' Q0'Q1'+xQ1'Q0+x'Q1Q0 +x'Q1Q0' Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'01 0 0 1 x11 0 0 1 Q0N( x, Q1,Q0) = Q0'Introduction to Digital Logic with Laboratory Exercises103 A Global Text PAGE 104 Appendix F: Solutions 7. (a) (b) Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'00 1 1 0x10 1 0 1 Q1N(x, Q1, Q0) = x' Q0 + Q1'Q0 + xQ1Q0 Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'01 1 0 0 x11 0 0 1 Q0N( x, Q1,Q0) = x' Q1' + xQ0' 104 PAGE 105 This book is licensed under a Creative Commons Attribution 3.0 License Index555 .............................................................................................................................................. 7, 37pp., 52, 74 7400 series .......................................................................................................... 7, 13pp., 17p., 20, 33, 54, 74p. Boolean algebra ...................................................................................................................................... 17, 19p. Breadboard ...................................................................................................................... 10pp., 16, 19, 24p., 74 Circuit diagram ........................................................................................................ 12, 14, 16pp., 24pp., 46, 56 Clock ............................................................................................................ 7, 14, 37pp., 42p., 45pp., 55pp., 62 Combinatorial logic ........................................................................................................................................ 44 De Morgan's law .............................................................................................................................................. 19 Debounced switch .................................................................................................................................. 55p., 74 DIP ............................................................................................................................................................. 14, 25 Don't care .................................................................................................................................... 27, 29p., 57pp. Edge triggered ............................................................................................................................... 45pp., 50, 56 Flipflop ...................................................................................................... 7, 44pp., 50pp., 54, 56pp., 62p., 74 Frequency ....................................................................................................................................... 37pp., 42, 51 Inverter ..................................................................................................... 10, 12pp., 17, 20p., 24pp., 40, 52, 74 Kmap ....................................................................................................... 20pp., 25pp., 32, 36, 52p., 57pp., 62 Karnaugh map .......................................................................................................................................... 20, 27 Latch ...................................................................................................................................................... 7, 44pp. Multiplexer .......................................................................................................................................... 32pp., 74 NAND ......................................................................................... 12p., 15, 17pp., 24pp., 32, 34, 45, 47, 52p., 74 NOR ................................................................................................................. 12p., 15, 18, 20, 25, 44p., 48, 74 Period ........................................................................................................................ 38pp., 42p., 46, 51, 56, 62 RAM ................................................................................................................................................................ 44 Resistor ............................................................................................. 7, 12, 14, 17, 37pp., 41pp., 55, 57, 69p., 74 Sequential logic ......................................................................................................................................... 44, 49 State machine ................................................................................................................ 7, 49pp., 57p., 60, 62p. State transition diagram ............................................................................................... 49pp., 53, 56pp., 60pp. Timer ........................................................................................................................... 7, 37pp., 42p., 49, 52, 74 Timing diagram .............................................................................................................................................. 39 Transistor ........................................................................................................................... 7, 10pp., 17, 37p., 74 Truth table .................................................................................... 12p., 15pp., 20pp., 24p., 33, 35p., 51, 53, 60 XOR ........................................................................................................................................................... 17, 20Introduction to Digital Logic with Laboratory Exercises105 A Global Text 