Analysis and modeling of stress related effects in scaled silicon technology


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Analysis and modeling of stress related effects in scaled silicon technology
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viii, 166 leaves : ill. ; 29 cm.
Chaudhry, Samir, 1969-
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Electrical and Computer Engineering thesis, Ph. D
Dissertations, Academic -- Electrical and Computer Engineering -- UF
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Thesis (Ph. D.)--University of Florida, 1996.
Includes bibliographical references (leaves 160-165).
Statement of Responsibility:
by Samir Chaudhry.
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I would like to thank my adviser, Dr. Mark E. Law, for his support, guidance, and

encouragement throughout my graduate school career. His boisterous laugh (which could

be heard in my office from time to time) and cheerful disposition was in its own way

responsible for tiding me over the slow months. I am grateful to Drs. Jerry G. Fossum,

Robert M. Fox, Kevin S. Jones, and Toshikazu Nishida for their guidance and support as

members of my doctoral supervisory committee.

I am grateful to the Semiconductor Research Corporation for their financial support;

Keith Rambo, James Chamblee, Steve Schein, and Viswanath Krishnamoorthy for their

technical guidance during the experiments; Jinning Liu and Robert Thompson for the

TEM data; Mary Turner and Glenda Miller for administrative help; and Stephen Cea for

the finite element code in FLOOPS and the extensive technical discussions on "stress."

My stay in Gainesville would not have been very enriching without my "happy-

hour" colleagues and officemates; Jonathan Brodsky, Ming-Yeh Chuang, Omer Doku-

maci, Hernan Rueda, Doug Weiser, Glenn Workman, Ping-Chin Yeh, and David

Zweidinger. I was fortunate to have two excellent roommates during my stay in Gaines-

ville; Srinath Krishnan, whose friendship I shall cherish for a long time to come, and

Noshir Tarapore, who taught me to smile through adversity.

It was my great fortune to have the love and guidance of my parents, Sandesh and

Indar Chaudhry, throughout my life. Without their support this dissertation would not have

existed. I would like to thank my sister and brother-in-law, Smriti and Sanjay Khetarpal,

for their love and for helping me settle down in the United States. Finally, I would like to

acknowledge the unconditional love and support of my dear fiance, Zareen Tarapore. She

not only proofread this dissertation, but was a source of inspiration throughout my doc-

toral research.

ACKNOWLEDGEMENTS ........................................................................................... age

ACKNOW LEDGEM ENTS ................................................ .............................................. ii

ABSTRACT ................................................................................................................... vii


I INTRODUCTION .......................................... ................................................ 1

1.1 Stress and Strain ........................................................................................ 3
1.2 Stress Related Issues in Silicon Technology ........................................... 8
1.2.1 Stress from Therm al Processing ......................................................... 9
1.2.2 Film Stress and Film Edge Induced Stress ......................................... 10
1.2.3 Stress from Isolation Trenches ............................................................ 13
1.2.4 Misfit Stress and Dislocation Generation in Epitaxial Silicon
W afers ................................................................................................. 15
1.2.5 Stress from Dislocation Loops ............................................................ 16
1.3 Organization .............................................................................................. 17

INERT AM BIENT ................................................................................................ 22

2.1 Experimental Details ................................................................................. 23
2.2 Experimental Results ................................................................................ 24
2.3 M odeling ................................................................................................... 30
2.3.1 M odeling the Loop Distribution ......................................................... 31
2.3.2 M odeling M echanism s of Loop Growth ............................................. 33
2.4 Two-Dimensional Growth of Loops Under a Nitride Mask ..................... 39
2.5 Summ ary ................................................................................................... 42

SILICON ............................................... ........................................................... 44

3.1 Experimental Details ................................................................................. 45
3.2 Experimental Results ................................................................................ 46
3.3 M odeling ...................................................................................................... 50
3.3.1 M odeling Loop Evolution from TEM Data ........................................... 51
3.3.2 M odeling the Strain from HRXRD Data ............................................ 53
3.3.3 The Effect of Boundary Condition ..................................................... 59

3.4 D ata A analysis ............................................................................................ 61
3.4.1 Correlation of Peak Strain with Captured Interstitials ........................ 61
3.4.2 Correlation of Peak Strain with Loop Density and Radius ................. 62
3.5 Pressure Profiling for Two-Dimensional Structures ................................. 62
3.6 Sum m ary ................................................................................................... 64

IV STRESS FROM THIN FILMS IN IC PROCESSING ................................... 65

4.1 Stress from Nitride Stripes ........................................................................ 68
4.1.1 Implementation in Finite Element Code ............................................. 69
4.1.2 A Single Nitride Stripe ........................................................................ 69
4.1.3 Stress from Multiple Nitride Stripes ................................................... 70
4.1.4 Stripe Width Dependence of Stress from Multiple Stripes ................. 75
4.1.5 Shear Stress in Substrate from Multiple Nitride Stripes ..................... 77
4.1.6 Film Thickness Dependence of Stress from Multiple Stripes ............ 79
4.1.7 Film Thickness Dependence of Shear Stress ...................................... 83
4.2 Wafer Curvature Due to Lattice Mismatch ............................................... 84
4.3 Sum m ary .................................. .............. ................................................. 90

DEPOSITED NITRIDE STRIPES ................................................................. 92

5.1 Effect of Patterned Nitride Stripes on the Diffusion of Phosphorus
in S ilicon ............................................................................................. ...... 96
5.1.1 Experim ental D details ........................................................................... 96
5.1.2 Junction Staining ................................................................................. 99
5.1.3 Experimental Results and Analysis .................................................... 101
5.2 Effect of Patterned Nitride Stripes on the Evolution of Dislocation
L oops in Silicon ........................................................................................ 105
5.2.1 Experim ental D details ........................................................................... 105
5.2.2 Transmission Electron Microscopy .................................................... 106
5.2.3 Experimental Results and Analysis .................................................... 115
5.3 Sum m ary ...................................... ............. .............................................. 118

ON POINT AND EXTENDED DEFECTS .................................................... 119

6.1 Simulation of Stress-Assisted Evolution of Dislocation Loops ................ 119
6.1.1 Sim ulation Structure ........................................................................... 122
6.1.2 Stress Field in the Substrate ................................................................ 123
6.1.3 Point Defect Concentrations in the Bulk ............................................ 124
6.1.4 Simulation of Average Radius of Loops ............................................. 126
6.1.5 Simulation of the Total Density of Loops ........................................... 128
6.1.6 Simulation of the Total Number of Captured Atoms .......................... 130
6.2 Simulation of the Stress-Assisted Diffusion of Phosphorus ..................... 131
6.2.1 Sim ulation Schem e ............................................................................. 133

6.2.2 Simulation Results and Analysis ........................................................ 135
6.2.3 Validity of Extracted Volumes ........................................................... 138
6.3 Effect of Stress on Device Characteristics ................................................ 146
6.4 Summ ary ................................................................................................... 148

FUTURE W ORK ............................................................................................... 149

7.1 Summ ary ................................................................................................... 149
7.2 Conclusions and Recommendations for Future Work .............................. 153

APPENDIX .................................................................................................................... 158
REFERENCES ........................................................................................................ 160
BIOGRAPHICAL SKETCH ...................................................................................... 166

Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy




August 1996

Chairman: Dr. Mark E. Law
Major Department: Electrical and Computer Engineering

Based on the current understanding of stress related problems in silicon technology,

the critical sources of stress in the silicon substrate are identified as ion-implanted disloca-

tion loops, patterned and continuous thin films, and lattice mismatched epitaxial films.

The stress from dislocation loops is found to be a strong function of the dislocation

loop ensemble properties. A model based on the Ostwald ripening phenomenon is devel-

oped to predict the evolution of dislocation loops in an inert ambient. Bounds for a critical

radius, below which the dislocation loops dissolve and shrink, and above which they grow,

are defined. The stress from a given ensemble of dislocation loops is modeled by calculat-

ing the extra number of atoms in the silicon substrate. This is used as an initial loading

strain force in a finite element solver to predict the stress in the substrate. The peak value

of the strain is experimentally verified using x-ray rocking curve analysis. The tensile

component of the substrate stress at the loop layer edges is found to be strongly sensitive

to the displacement boundary condition at the lateral edges of the simulation structure.

A numerical model, based on a balance of forces finite element solver, is developed

to predict the stress in the silicon substrate from patterned and continuous films. The

intrinsic or thermal mismatch stress is used as a initial loading condition on the structure.

The wafer bow predicted by the model is in agreement with the experimentally extracted


The effect of stress from multiple nitride stripes on the diffusion of phosphorus and

the evolution of dislocation loops is experimentally investigated. As compared to the

tensed regions of the substrate, regions of compression show retarded diffusion of phos-

phorus, and a smaller size and density of the dislocation loops. A simulation scheme is

developed to investigate the main mechanisms responsible for this anomalous behavior.

Based on the results of the simulations, upper bounds for the elastic inclusion volumes of

point defects and dopant-point defect pairs are extracted.


The reduction in active device dimensions to micron and sub-micron geometries has

resulted in an intimate coupling of process conditions, device behavior, and circuit perfor-

mance to a degree unknown a few years ago. Due to the inherent complexity of integrated

chip (IC) processing, it is becoming progressively more difficult to develop new processes.

A modem IC process contains several hundred individual steps. The use of computer

aided design tools has proven to be invaluable in new technology development and IC

design. Computer simulations have also emerged as a very elegant way to aid process and

device engineers in their task of finding an optimum process for a given device or circuit


The traditional "trial-and-error" experimental approach used to develop new tech-

nologies starts with an existing process. Together with structural dimensions, certain pro-

cess steps are then altered to fabricate several lots. Completed test structures are

subsequently evaluated to investigate if the original goals have been met. In Figure 1.1,

route A schematically describes this approach, which might require several iterations to

optimize the new process [1].

The application of software tools in the development of new processes and novel

device structures has become a worthwhile, albeit challenging, alternative to the experi-

mental route (see path B in Figure 1.1). Fabricating one lot in a modem process can cost

upwards of 10,000 dollars, and consume weeks or even months of effort. The use of accu-

rate simulation tools in the proper computing environment allows for comparatively inex-

pensive "computer experiments."

Figure 1.1 Simulation and experiment as alternative routes in development of new tech-
nologies. Route B would eventually involve a run through Route A, but helps in consider-
ably lowering the time and expense of Route A.

Figure 1.2 Process simulation as part of the general simulation methodology.

Figure 1.2 schematically illustrates the various software aids for IC technology

development. Process simulation deals with all aspects of IC fabrication. With the proper

input parameters (process recipes, layout geometries), process simulation determines the

details of the resulting device structure, such as the boundaries of different materials and

the distribution of impurity ions.

The complex fabrication technique used to make the modem day silicon IC involves

the contiguous embedding, butting, and overlaying of structural elements. Such elements,

with vastly different thermal and elastic properties, develop stress during the thermal

cycling of the chip. Furthermore, many of the materials used in silicon technology such as

CVD (Chemical Vapor Deposition) silicon nitride, silicon dioxide, polycrystalline silicon,

etc., by virtue of their formation processes, exhibit intrinsic stresses. Large localized

stresses are induced in the silicon substrate near the edges and comers of such structural

elements. Oxidation of non-planar surfaces, frequently encountered in ULSI (Ultra Large

Scale Integration) processing, produces another kind of stress in the substrate that can be

very damaging, especially at low oxidation temperatures. Mismatch of atomic sizes

between dopants and silicon atoms produces another kind of strain that can lead to the for-

mation of misfit dislocations.

1.1 Stress and Strain

Before proceeding with a discussion on some of the stress related issues in silicon

technology, this sections reviews the fundamental physics associated with studying mate-

rial deformation.

F F=oA F

Figure 1.3 Figure illustrating the idea of stress: a body to which a stretching force is

The basic idea of stress can be understood by considering a body (Figure 1.3) to

which a stretching force F is applied. The force has a tendency to "stretch" the specimen,

breaking the internal bonds. The bond-breaking is opposed by internal reactions in the

body, called stresses.

The best way of visualizing these stresses is by the method of analysis used in

mechanics of materials: the specimen is "sectioned" and the missing part is replaced by

the forces that it was exerting (Figure 1.3). In this case the "resistance" is uniformly dis-

tributed over the normal section, as shown by the two arrows. The normal stress a is

defined as the "resistance" per unit area. Applying the equilibrium of forces principle to

the right side portion of the specimen:


F- aA = 0 1-1

Y = F/A

This is the internal resisting stress opposing the externally applied load, thereby

preventing the sample from fracturing. As the applied force F increases, so does the

length of the specimen. For an increase of dF, the length I increases by dl. The

normalized (per unit length) increase in length is equal to

de = dl/1 or integrating = f dl/1 = In 1-2

where 10 and 11 are the initial and final lengths of the specimen, respectively, and E is the

longitudinal strain.

Another frequent form of deformation commonly encountered in semiconductor

engineering is the shear strain. To illustrate shear, consider a circular cylindrical shaft, as

shown in Figure 1.4 (a). When the shaft is twisted, the elements in the shaft are distorted in

the manner shown in Figure 1.4 (b). In this case the angle a may be taken as a measure of

the strain. However, it is customary to treat tan a as the shear strain.


(a) (b)
Figure 1.4 The shear pattern of deformation (a) twisting, and (b) simple shear.

The selection of proper measures of strain is dictated basically by the stress-strain

relationship (i.e., the constitutive equation of the material). For example, if we pull a

string, it elongates. The experimental results can be presented as a curve of the tensile

stress a plotted against the strain e. An empirical formula relating a to e can then be

determined. For most engineering materials subjected to infinitesimal strain in uniaxial

stretching, a relation, like

a = E 1-3

where E is a constant called Young's modulus, is valid within a certain range of stresses.

Equation 1-3 is called Hooke's law, and a material obeying it is called a Hookean material.

Corresponding to Equation 1-3, the relationship for a Hookean material subjected to an

infinitesimal shear strain is

T = G tan a 1-4

where G is another constant called the shear modulus or modulus of rigidity. The range of

validity of Equation 1-4 is again bound by a yield stress, this time in shear. The yield

stresses in tension, compression, and in shear are generally different. Deformations of

most materials in nature and in engineering are much more complex than those discussed.

Therefore, general method of treatment is needed. However, the general mathematical

description of deformation is described first.

Let a body occupy space S. Referred to a rectangular cartesian frame, every particle

in the body has a set of coordinates. When the body is deformed, every particle takes up a

new position, described by a new set of coordinates. For example, a particle P, located

originally at a point (a, a2, a3) is moved to a point Q (xl, x2, x3) when the body

moves and deforms. The vector PQ (Figure 1.5) is called the displacement vector of the

particle under consideration, and its components are

x, -a1, x2- a2, x3- a3 1-5

X2, X3)


Figure 1.5 Displacement vector of a body that has been moved and deformed.

If the displacement is known for every particle in the body, the deformed body can

be constructed from the original structure. Hence, the deformation can be described by a

displacement field. Let the variable (al, a2, a3) refer to any particle in the original con-

figuration of the body, and let (x1, x2, x3) be the coordinates of that particle when the

body is deformed. Then the deformation of the body is known if (x1, x2, x3) are known

functions of (al, a2, a3) :

xi = xi(a1, a2, a3) 1-6

This is a transformation (mapping) from (a, a2, a3) to (xl, x2, x3) Subject to the

assumptions of continuum mechanics, the displacement vector u is then defined by its

components ui = xi- ai.

1.2 Stress Related Issues in Silicon Technology

Stress related problems are pervasive and critical in ULSI technology. Many prob-

lems of defective devices in silicon integrated circuits can be ultimately traced to stresses

that develop at various stages of I.C. processing. These problems grow more acute as I.C.

devices become smaller in size and more complex in geometry and material mix. It is thus

important to understand the nature and the origins of these problems. A clear understand-

ing of these effects would aid engineers attempting to alleviate stress related problems in

silicon technologies. In addition, quantitative modeling of these effects would be useful in

designing processes and devices for optimal performance. The following sections attempt

to bring out the origins of the aforementioned stress problems and their possible effects on

device properties.

1.2.1 Stress from Thermal Processing

One class of stress problems, called thermal stress, arises from nonuniform tempera-

ture distribution within a silicon wafer. It remains an ever present problem in IC thermal

processing, where transient temperature gradients are produced in silicon wafers during

heating up and cooling down. The main symptoms of this problem were wafer warpage

and slips and emerged when the size of the silicon wafer was increased from I to 2 inches.

This problem was first recognized and analyzed in detail in 1969 by Hu [2] with the intro-

duction of the concept of radiative heat transfer. In his model, an area element dA emits

radiant energy at a rate that is proportional to the fourth power of its absolute temperature.

The same area element also receives radiant energy from all area elements dA' in each of

the two immediately neighboring wafers; these elements being at different temperatures

over the entire wafer area A'. If the row of wafer is assumed to be infinitely long, then the

temperature distribution in the two neighboring wafers is exactly the same as that in the

subject wafer. The analysis reveals that the central region of the wafer cools down or heats

up more slowly than the outer regions, setting up a radial temperature gradient, whose

magnitude increases with the rate of heating or cooling. The maximum transient tempera-

ture difference between the center and edge of the wafer also increases with processing

temperature and with the wafer diameter to spacing ratio. Various extensions to Hu's anal-

yses have been made over the years [3,4].

At some stage during cooling, the thermal stress may exceed a threshold and is

relieved via plastic deformation. At the final room temperature, the plastic strain intro-

duced during cooling becomes frozen in, causing stress to be developed with a radial dis-

tribution which is approximately a reverse of that existing when the plastic deformation

took place. Analyses [2,5] have shown the wafer will then warp with an anticlastic geome-

try; a universal saddle shape for <100> wafers.

1.2.2 Film Stress and Film Edge Induced Stress

Another class of stress problems arise when films such as silicon dioxide, silicon

nitride, aluminum, or polycrystalline silicon are overlaid on silicon substrates [6]. Stress

exists in these films both because of their thermal expansion mismatch and mechanistics

of the film growth processes. Stress from the latter source is called "intrinsic stress." Con-

tinuous films produce only very low levels of stress in the substrate. This is because the

substrate is usually about three orders of magnitude thicker than the surface films, and

consequently, the stress level in the silicon substrate is lower than the film stress (as large

as a few GPa) by three orders of magnitude. Problems occur when the surface films are not

planar or contain certain discontinuities such as window edges. These discontinuities pro-

duce large localized stresses in the silicon substrates.

Direct dislocation generation at the edges of polycrystalline silicon stripes on silicon

dioxide has been reported for charge coupled (CCD) devices [7]. Direct dislocation gener-

ation at the nitride edge has been observed [8] for film thicknesses larger than 200 nm

deposited on bare silicon. These are usually 600 dislocations, and when the nitride edge is

not in the <110> direction, form loops that straddle the edge. If there is a pad oxide layer

between the silicon nitride film and the silicon substrate, no dislocation is directly gener-

ated when heat treated in a nitrogen ambient at temperatures as high as 11000C [8].

Though a thicker pad oxide could be used to alleviate the harmful effects of stress in

the substrate, it makes the nitride a less effective diffusion mask when used in an isolation

scheme called local oxidation of silicon (LOCOS), and leads to a longer "bird's beak."

The bird's beak which forms an unintended oxide wedge between the silicon nitride edge

and the silicon substrate, stands in the way of device size reduction. The minimum thick-

ness of the pad oxide required to prevent the formation of defective oxides has been stud-

ied by Bogh and Gaind [9] and Magdo and Bogh [10]. Much thinner pad oxide

requirements have also been reported [11].

Dislocation generation due to nitride edges frequently occurs via indirect means.

Thermal oxidation of silicon generates interstitials, some of which drift to the nitride edge

and help nucleate dislocation loops there [12 14]. Bogh and Gaind [9] observed the for-

mation of loops under nitride edges when the anneals were carried out in an oxidizing

ambient. However, loops were absent in samples annealed in a nitrogen ambient for nitride

thicknesses upto 166 nm.

In their study Hu and Schwenker [15] demonstrated the interaction of point defects

with a nitride film edge. Point defects introduced in the substrate via ion-implantation

formed dislocations which were clustered around the edge of the nitride stripe. Regions

masked out from the ion-implantation showed no such dislocations. Another frequently

observed process by which dislocation loops are generated at nitride edges was proposed

by Hu et al. [16]. An inclined edge or 600 dislocation introduces an extra half lattice plane

that extends either obliquely upward or downward. The dislocation is attracted to the

nitride covered region if the extra half plane extends upward and is repulsed when the

extra half plane extends downward. Figure 1.6 illustrates how a film edge induced stress

field interacts with a moving dislocation. A dislocation, travelling to the right, introduces

an oblique extra half plane that extends downward. It experiences repulsion at the nitride

edge and starts to bend upward, inverting the sense of its associated half plane which is

now obliquely upward. The right hand side dislocation half loop, in contrast to the left seg-

ment, now experiences a driving force to the right, so that the loop gets pulled out at both

ends and cannot collapse despite the line tension. It then permanently straddles the film

edge. The dislocation loop so generated is occasionally referred to as the "Hu" loop [17].

a b c


Figure 1.6 A frequently occurring mechanism of creation and trapping of dislocation
loops through the interaction of a film edge induced stress field with a travelling disloca-
tions. A gliding dislocation approaches the nitride edge (a), experiences the stress field
induced force and begins to bend (b), (c), and continues to glide on after shedding a dis-
location loop L (d), interacts attractively with the left side edge stress field (e), and
repeats the cycle (f). [From reference 17]

The straddling configuration of the loop shown in Figure 1.6 is especially deleteri-

ous to devices like transistors. The travelling dislocation may continue to glide till it

comes to its final position, determined by the macroscopic stress fields such as thermal

stresses. This mechanism of defect generation has been frequently observed in devices

using LOCOS as the isolation technique [18-20]. It also operates in the generation of

"emitter-edge-defects" [16] through interactions with gliding thermal slip dislocations.

Stress from multiple and periodically patterned nitride stripes is studied using the

finite element method in Chapter IV. The effect on point defects and extended defects is

also presented. As the devices get scaled and the geometries get more complex, robust

simulation of stress from thin films will become essential. The methodology developed to

simulate such stresses encompasses a wide array of structures and provides both qualita-

tive and quantitative insight into the physics.

1.2.3 Stress from Isolation Trenches

As new generations of integrated circuits evolve, two major trends are evident: the

packing density on a chip increases, and device dimensions are reduced. Higher packing

densities are achieved by making devices smaller and by packing them closer together.

One prime requirement for these closely packed devices is the need for good electrical iso-

lation. In general, as the area available for isolation has reduced the stress levels in the

substrate have risen [21]. Also, as the active device regions are brought closer to the isola-

tion structures, control of dopant diffusion in these regions becomes difficult.

(a) (b) (c)
S mI I


I Oxide

Figure 1.7 Deep trench fabrication sequence: (a) trench is formed by RIE, followed by
(b) oxidation, and (c) removal of oxide at bottom of trench, filling with polysilicon, and
planarizing. From reference 21.

Stress from isolation structures like trenches, and V-grooves has been investigated

both experimentally [21, 22] and by using finite element analysis [23, 24]. Fahey et al.

[21] pointed out the disadvantages of using low thermal budgets in the drive to form shal-

low junctions. The oxide, with a lower viscosity at these low temperatures, is unable to

deform, thereby transferring an enormous stress on to the silicon substrate. Typically,

reactive ion etching is used to form isolation trenches in silicon technology (Figure 1.7). A

thin layer of thermal oxide is then grown on the trench sidewalls. The trenches are finally

filled with Chemical Vapor Deposited (CVD) silicon dioxide or another CVD dielectric.

CVD polysilicon, though not a dielectric, is frequently used in place of the CVD silicon

dioxide. High levels of stress at the trench corners can be generated during thermal oxida-

tion, though the use of very thin oxides can alleviate this problem. During thermal treat-

ment thermal expansion mismatches between silicon and the trench-fill material can lead

to significant stresses. For example, the thermal expansion coefficient of silicon dioxide is

nearly an order of magnitude smaller than that of silicon. Intrinsic stresses of the CVD

materials can also be a problem.

Hu [25] investigated and summarized [17] a large number of cases of stress from

isolation techniques. He showed that for an oxide trench-fill that expands against the

trench wall, a compressive stress component exists in a direction perpendicular to the

trench sidewall. This stress is predominantly localized near the bottom part of the trench

sidewall, and near the surface region. The stress component parallel to the trench sidewall,

is generally tensile and localized near the center of the sidewall. The shear component of

the stress is almost absent at the mid-length of the trench and becomes dominant only near

the trench end.

1.2.4 Misfit Stress and Dislocation Generation in Epitaxial Silicon Wafers

A large lattice interfacial mismatch occurs when a lightly doped epitaxial (epi) layer

is grown on top of a heavily doped substrate. For example, if the substrate is doped with

1018 ~ 1019 /cm3 boron and the lightly doped epi has boron in concentrations of the order

of 1015 /cm3, a lattice mismatch of approximately 0.028 A is present at the interface of the

epi and the substrate [26]. The resulting stress that occurs during the CVD deposition of

the epi is tensile on the epi side, while the substrate is in compression. If this stress is

below a certain threshold, the system relaxes by wafer bowing, and if above it, disloca-

tions are generated. A large wafer bow is undesirable from the lithographic view point,

while the dislocations might cause yield related problems.

A part of the problem can be alleviated by a phenomenon called "compensation,"

where the heavily doped substrate is "grown" with a solute which causes the lattice con-

stant of silicon to change. Lin et al. [26] demonstrated this concept by incorporating ger-

manium during the wafer-melt process in the heavily doped substrate. As opposed to

boron, germanium causes the lattice constant of silicon to increase. It was also determined

that a germanium to boron concentration ratio of 6.8 could bring about complete compen-

sation in the silicon lattice. The lightly doped epitaxial layer can then be grown on top of

the boron doped substrate with minimal misfit at the interface.

1.2.5 Stress from Dislocation Loops

High dose ion-implantation is frequently used to define regions like the source and

drain in a MOSFET, and the emitter regions of a bipolar transistor. Though this procedure

controllably produces the desired doping levels and junction depths, it amorphizes the

region it is implanted in. During subsequent annealing this amorphized region

recrystallizes to form end-of-range dislocations at the original amorphous-crystalline

interface. Unlike point defects, extended defects such as dislocation loops are large

enough to be observed by techniques such as Transmission Electron Microscopy (TEM).

Using this technique Jones et al. [27] analyzed the morphological characteristics of the

extended defects due to ion-implantation in silicon. They observed a strong dependence

on the species, dose and energy of the implant. The anneal characteristics were strongly

governed by the time and temperature of the thermal cycle.

If uncontrolled, dislocation loops can affect the final properties of the device. A sig-

nificant leakage current is known to exist if the dislocations are located across junc-

tions[28]. If the dislocations are located outside the space charge regions, the device

operation is not affected. Dislocation loops affect dopant redistribution during thermal

cycling by capturing and emitting point defects. This might lead to major variations in

junction depths. Dopant profiles in the device are also influenced by the stress field associ-

ated with the loops. A compressive stress field leads to an undersaturation of interstitials,

thereby retarding diffusion of dopants like boron and phosphorus, which rely on intersti-

tials for diffusion.

1.3 Organization

This work attempts to analyze and model stress effects in scaled silicon device tech-

nology. Based on the current understanding of point defects and their interaction with

stress fields, an effort is made to identify critical stress inducing sources, model the char-

acteristics of these sources and then apply the results to understand the effects on current

and future semiconductor device technologies. This work also brings out the critical issues

and limiting factors that affect modern process design. Relevant physics is incorporated

wherever the need exists. Numerical simulations are resorted to for complex problems,

and their results are qualitatively explained. Experimental verification is performed for

most of the simulated data.

Chapter II

Chapter III

Chapter IV,V & VI

Figure 1.8 Stress effects in silicon studied as part of this dissertation.

Figure 1.8 illustrates the stress effects in scaled silicon technologies studied as part

of this dissertation. The sources of stress are classified and studied as part of different

chapters. Chapter II looks at the evolution of dislocation loops in an inert ambient. Since

the loops affect dopant profiles, information about their size and density are important for

a process engineer. This chapter develops point defect based two-dimensional models for

the evolution of loops in an inert ambient. The Ostwald ripening process, where large

loops grow at the expense of smaller ones, is the basis of the model developed. Loop evo-

lution as observed under TEM analysis is used to verify the accuracy of the model. The

model is subsequently used in Chapters III and VI.

Knowledge of the stress from a given dislocation loop ensemble is important for

process modeling. There are two major consequences of this stress. First, it is the driving

force for the movement of point defects into and out of the ensemble. Second, the stress

can affect dopant diffusion in regions close to the ensemble. A model for stress due to the

dislocation loops based on the widely used finite element analysis is developed as part of

Chapter III. The effect of boundary conditions is studied, and the current status of the

investigations brought out. X-ray rocking curve analysis is used to obtain peak values of

strains in the substrate. These are then compared to the simulated values. The simulations

provide the user with the means of profiling the stress in the substrate, not possible with

the rocking curve experiments.

Stress from thin films is the focus of Chapter IV. The effect of multiple nitride

stripes on the silicon substrate is studied. The stress in the bulk is characterized as a func-

tion of stripe width and thickness. The results of this chapter lay the groundwork for the

design of the experiment for Chapter V and the simulation scheme of Chapter VI.

Wafer curvature due to lattice mismatch between epitaxial layers and the substrate is

modeled and compared to available experimental data as a second part of Chapter IV.

Large wafer bow is undesirable due to lithographic limitations. A phenomenon called

"compensation," which has been successfully used to minimize the bow, is simulated. This

provides the user with a predictive capability to optimize this process.

Based on the results of Chapter IV, an experiment is designed to investigate the

effect of stress from patterned nitride stripes on point and extended defects in Chapter V.

Phosphorus is used as a representative dopant to investigate the effect on point defects.

High dose ion-implantation is used to introduce dislocation loops in the substrate. These

loops are then annealed in the presence of the nitride stripes. Plan view TEM (Transmis-

sion Electron Microscopy) is used to extract the size and density characteristics of the dis-

location loop ensemble. The results are analyzed and qualitatively explained. The

experiment design includes splits on stripe widths and thicknesses, and anneal conditions,

to bring out the corresponding dependencies.

Chapter VI quantifies the results of Chapter V. It integrates the models developed in

this work and verifies them with the experimental data. The models for stress from Chap-

ter IV are used to simulate the stress-assisted diffusion of phosphorus. The same models

are integrated with loop evolution models (Chapter II), and loop stress models (Chapter

III), to predict the stress-assisted evolution of ion-implanted dislocation loops. Experimen-

tal data from Chapter V and the work of other researchers is used to estimate the upper

bounds for the fundamental parameters used to optimize the simulations. Using these

extracted parameters the effect of stress on a scaled ULSI MOS device is simulated. The


change in threshold voltage of the device as a function of the substrate stress is extracted

using a device simulator.

Some of the important contributions of this work are summarized in Chapter VII.

Based on the trends in modem ULSI technology some of the results are extrapolated with

sound reasoning. Finally, some recommendations are made regarding possible future

directions to the research in this field.


The use of high dose ion-implantation, to obtain heavily doped regions in silicon

such as the source and drain of a MOSFET, has gained immense popularity in the last two

decades due to the inherent controllability of the implanted profile. However, the damage

created in the substrate by this process strongly affects dopant redistribution during later

anneals. During the anneal, solid phase epitaxial regrowth of the amorphized region leads

to the formation of end-of-range dislocation loops at the amorphous/crystalline (a/c) inter-

face. It has been shown that the end-of-range dislocation loops affect the distribution of

point defects by the absorption of interstitials or emission of vacancies at their core bound-

ary during growth and by the reverse process during shrinkage [29, 30].

Earlier work [31-34] established theoretical models for a single circular dislocation

loop and its interaction with point defects. Bullough et al. [32] used Bastecka and

Kroupa's [33] stress field solution to predict the migration of a single interstitial atom

around a single dislocation loop. Borucki [34] proposed a model for the growth and

shrinkage of a single dislocation loop due to the capture and emission of point defects, and

simulated the point defect variation from an assumed initial high supersaturation around a

periodic array of the loops in a three dimensional numerical solver of diffusion equations.

Park, Jones, and Law [29] developed a statistically based model for loop growth in an oxi-

dizing ambient, where the interstitials injected from the growing oxide contribute to the

growth of the large loops. Pressure effects from the loops were incorporated into the point

defect equations. Liu [35] demonstrated that in an inert ambient loop growth kinetics are

mainly governed by loop-to-loop interactions, with the large loops growing at the expense

of smaller ones (Ostwald ripening). This work quantitatively analyzes the size and density

distribution of the loops as a function of anneal time and temperature.

2.1 Experimental Details

The experimental procedure was designed and executed by Liu [35]. Czochralski

single crystal silicon wafers (<100> orientation, boron doped (l-100 Q cm), 600-650 gm

thick) were used as the starting material. Si+ ions were implanted at 50 keV and a dose of

lxl015/cm2 into the silicon substrate. The implant temperature was kept constant around

room temperature and was stabilized during implantation using a way-flow freon cooled

end-station. A dose rate of 20 gA was maintained throughout the implantation process. A

continuous amorphous layer was formed as a result of the implantation. Upon annealing

type-II or EOR (end-of-range) [27] dislocation loops were formed just below the amor-

phous/crystalline interface (-1200 A deep), as determined by cross-sectional TEM mea-


After implantation, the entire wafer was capped with 6000 angstroms of SiO2 before

the annealing process to limit any oxidation in the inert ambient. The wafers were then cut

into four parts and annealed in a nitrogen ambient at 700, 800, 900 and 10000C for times

ranging from 15 minutes to 16 hours. The capped oxide for all samples was removed by

HF before mechanical and jet etching. The total loop density, the average loop size, the

loop distribution and the interstitials bound by loops were measured under plan view TEM

on a JEOL 200CX TEM.

2.2 Experimental Results

The loop distribution N(r) versus loop radius r is shown for the various anneal con-

ditions in Figure 2.1 to Figure 2.4. N(r) represents the loop density at radius r. A shift in

the loop distribution towards a larger radius is observed with increasing time for each tem-

perature. The velocity of this movement is smaller for the low temperature anneals. This is

the result of the loop coarsening process. Since N(r) is proportional to r2, the plot for large

r is expected to show considerable scatter, particularly when the number of loops counted

is relatively small, as in the case of the 10000C anneal. If the temperature is kept constant,

the loop size increases with anneal time, although at low temperatures (700-8000C) this

movement is much slower than at high temperatures (900-10000C). The total loop density

decreases for increasing anneal time, causing the density of interstitials bounded by the

loops to remain constant (at low temperatures) or to decrease (at high temperatures). For

annealing times greater than 2 hours at 10000C stacking faults are formed.

The average loop radius is measured for each anneal condition. Figure 2.5 shows the

average loop radius versus anneal time at different temperatures. An increase in the aver-

age loop radius is observed with increasing anneal time, though this rate of increase is

quite slow at the lower temperatures. At the early stage of the 7000C anneal, the loops are

quite small. However, after 4 hours of annealing they are well developed. Also, with

increasing anneal temperature, the average loop radius increases. This means that more of

the implantation induced supersaturated interstitials move to the dislocation loops at the

higher temperatures.

15 min.


1E10 --
14 34 69 103

1 hour




4 hours



30 min.


2 hours

14 34

69 103

16 hours



Figure 2.1 Size spectra of loops as a function of loop radius after annealing in nitrogen at
7000C for different anneal times. The radius is in angstroms and the density is /cm2.





30 min.

1 E9
14 34 69 103 137 171

2 hours


16 hours

14 34 69 103 137 171

z1E10 -

14 34 69 103 137 171

Figure 2.2 Size spectra of loops as a function of loop radius after annealing in nitrogen at
8000C for different anneal times. The radius is in angstroms and the density is /cm2.

15 min.

I -1E10

1 hour

4 hours

15 min

E1i0 I L-

34 69 103 137 171 206

1 hour

4 hours

1E109 -

34 69 103 137 171 206

16 hours

1E8 1 1
171 206 240 274 308 343
SDsim lOexp

Figure 2.3 Size spectra of loops as a function of loop radius after annealing in nitrogen at
9000C for different anneal times. The radius is in angstroms and the density is /cm2.

30 min

2 hours

34 69 103 137 171 206

15 min.

100 150 200 250 300 350 400 450

30 min.

100 150 200 250 300 350 400 450

1 hour

100 150 200 250 300 350 400 450
Radius I Dsim Dexpi

Figure 2.4 Size spectra of loops as a function of loop radius after annealing in nitrogen at
10000C for different anneal times. The radius is in angstroms and the density is /cm .

The total loop densities are shown in Figure 2.6. A decrease in the densities is

observed with increasing anneal time. If the anneal time is kept constant, the density is

found to decrease with an increase in the temperature of the anneal. This implies that the

initial rate of dissolution of the smaller dislocation loops is more pronounced at higher

temperatures. At 10000C the total density of loops after a 15 minute anneal is several

orders of magnitude below the corresponding densities at the lower temperatures.

&-7000C Sim.
"7000C Exp.
i-1 8000C Sim.
M--M8000C Exp.
0-9000C Sim.
300.0 9000C Exp.
A-0-10000C Sim.
10000C Exp.

D 200.0-


0.0 200.0 400.0 600.0 800.0 1000.0
Time (minutes)
Figure 2.5 Plot depicting the increase in the average loop radius with increasing time for
temperatures ranging form 7000C to 10000C.

Loops begin their dissolution right after the 10000C anneal. For the 700 and 8000C

anneals, the loops remain in the coarsening regime and the densities of interstitials bound

by the loops remain fairly constant. For the 9000C anneal, the density of the captured

interstitials decreases with increasing time. However, the larger loops continue to grow,

while the smaller loops continue to shrink and eventually dissolve.




400.0 600.0
Time (minutes)


Figure 2.6 Experimental and simulated values of the total density of loops for various
anneal conditions, showing the decrease in density of loops with increase in either time
or temperature.

2.3 Modeling

The modeling strategy is a two-pronged one. A triangular distribution function

model for the dislocation loop distribution is used from Park et al. [29]. The loop






distribution is updated at each time step in the second part of the model by calculating the

loss of trapped interstitials from the smaller atoms and using it to calculate the increase in

size of the larger loops.

2.3.1 Modeling the Loop Distribution

As seen in the experimental data in Figure 2.1 to Figure 2.4, the loops distribution

can be modeled in the form of an asymmetrical triangular distribution function. Such a

model has been developed by Park, Jones and Law [29]. It assumes circular loops distrib-

uted on a plane interconnecting their centers. The orientation of the loops is assumed peri-

odic in two perpendicular directions. The radius and density are assumed to follow an

asymmetric distribution function. Each set of loop data is characterized by its minimum

radius (Rmin), its peak radius (Rp), where the density of the loops is a maximum (= D ),

and the maximum radius of the distribution (Rmax). The total density of the distribution is

represented by DaI. The unnormalized probability distribution function fd(R) is then

given as

2D i( R Rmi )
fd(R) = 2Dai(R Rrin) when Rmin < R < R 2-1
(Rmax Rmin) (Rp Rmin)

2Dal(Rmax R)
fd(R) (R R )(max R) when R < R < Rmax 2-2
(Rmax Rmin) (Rmax RP)

and the density at a particular radius D(R) is given as

D(R) = ARfd(R)dR' = fd(R)AR 2-3

The density Dp of the majority loops with radius Rp and its relation with the total density
DalI can be expressed by using Equations 2-1 to 2-3:

2DallR 2D al
Dp = fd(RP)AR = R ax l 2-4
Rmax -min m

where m is defined to be (Rmax Rmin)/AR = 2Da/D,, The average radius for a given
distribution is derived in Park et al. [29] as

Rave = (Rmin + R + Rx) 2-5

This model is described in detail in reference 29. The model is extended and suit-

ably modified to account for loop to loop interactions as observed in the experimental

data. Growth and shrinkage of the dislocation loops are modeled in terms of their reaction

with point defects at the loop layer boundaries. The boundary conditions are given by the

reaction rates of dislocation loops and the point defect formation energy change due to

loop growth or shrinkage. The interstitial continuity equation in the presence of disloca-

tion loops is derived in Park et al. [29] and is used the current model as well. It incorpo-

rates the variation in the local point defect concentrations due to emission and/or

absorption of interstitials/vacancies by the dislocation loop ensemble.

2.3.2 Modeling Mechanisms of Loop Growth

Growth of loops during a thermal anneal occurs via two main mechanisms [36]. The

first occurs via the migration of point defects to and from loops, and is called the bulk dif-

fusion mechanism. The second mechanism is due to the glide and self-climb of loops

resulting in the aggregation and coalescence of loops.

When the bulk diffusion mechanism is operative, loop growth or shrinkage occurs

by the diffusion of point defects to and from the loops via the substrate. For the case of

ion-implanted silicon the point defects that migrate are interstitials. The diffusion limited

change in loop radius, r, is then dr/dt = ADgrad(Ci), where A is a geometrical fac-

tor depending on the boundary conditions for diffusion, DI is the diffusivity of intersti-

tials, and C, is the concentration of interstitials.

The driving force for aggregation of loops by a combination of glide and self-climb

is provided by the elastic interaction existing between the loops. In this case a loop of

radius r, glides towards a loop of radius r2, r2 > rI, and coalesces with it to form a larger


The annealing behavior of type-II dislocation loops follows the Ostwald ripening

process of loop coarsening governed by a bulk diffusion phenomenon [35, 36]. In this pro-

cess the smaller loops shrink and eventually dissolve, while the larger loops absorb the

emitted interstitials and increase in size. Physically, this is because it is energetically more

favorable for a larger loop to increase in size and a smaller loop to dissolve.

The effective local equilibrium concentration of interstitials at the loop layer bound-

ary, CIb, is given [34, 37] as

Clb = gbcC*(p)exp(-AEf/kT) 2-6

Cb = C*(p)exp(AEf/kT) 2-7

where gbc is a geometric factor (=-0.3), C*I(p) is the pressure dependent concentration of

interstitials, k is the Boltzman's constant and T is the absolute temperature. AE, is the

change in defect formation energy due to the self-force of a dislocation loop during the

emission and absorption process at its edge:

AE = t RIn (8R 42-41 2-8
S 41t(I -v)R rc 4v-4

where g is the shear modulus, b is the magnitude of the Burgers vector of the loop, L2 is

the atomic volume of silicon, rc is the core (torus) radius of the loop, u is the Poisson's

ratio, and R is the radius of the dislocation loop. According to Equation 2-6, the concen-

tration of self-interstitials at the periphery of a dislocation loop of radius ri is lower than

that at the periphery of a loop of radius r2, when r, > r2 (Figure 2.7). Therefore, a gradient

in the concentration of self-interstitials is established between dislocation loops with dif-

ferent radii. This concentration gradient induces a self-interstitial flux from the smaller

loops to larger ones. As a result larger loops grow and smaller loops shrink until they

eventually vanish, in accordance with the Ostwald ripening phenomenon. This constitutes

the dislocation loop coarsening process.


Figure 2.7 Schematic diagram to illustrate the silicon self-interstitial concentration gradi-
ent established due to the size difference of the dislocation loops.

The radii and the density of the majority sized loops (or the unit distance L

between the loops) can be correlated with the number of silicon atoms bound by the dislo-

cation loops per unit area (n(Rp) ) by considering that the density of majority size loops

Dp is equal to 0.5 Lp2:

n(R) = (0.5 tnaR2)/L2 2-9

where na is the atomic density of Si atoms on the <111> plane (=1.5 x 1015 cm-2). If n, is

the density of interstitials bound at radius R of the ensemble, its time derivative should

equal the absorption of interstitials or the emission of vacancies at the loop layer bound-

aries, i.e.

a ann= aKIL(C Clb) aKVL(CV CVb)latRadiusR 2-10

where a is an effective cross section of the loop layer in the unit of linear length, KL is

the constant of reaction between the interstitials and the dislocation loop collection, KVL

is a similar constant for vacancies, C1/y is the concentration of interstitials/vacancies, and

CIb/vb are defined in Equations 2-6 and 2-7. It is apparent that during the coarsening pro-

cess the smaller loops loose silicon atoms to the larger ones. Thus the quantity on the left

in Equation 2-10 should be positive above a certain value of the radius (Rcrit), and nega-

tive below it, i.e.

> 0 for R > Rcrit 2-11

< 0 for R < Rcrit 2-12

Such results were confirmed using simulations in FLOOPS (Florida Object Oriented

Process Simulator). In this model the net loss of silicon atoms at an average size (=

(Rmin + R )/2 ) is estimated, and used to calculate the rate of growth of the loops of

radius R i.e.

an +n 2-13
R Rmin R +R

The relationship between the time derivatives of R and n is derived as

an an an+ dL 1Jt R 214

where the first two derivatives on the right are evaluated using Equation 2-9. Thus, Equa-

tions 2-13 and 2-14 give the time rate of change of the peak radius, which is then used to

obtain the time rate of change of the other distribution parameters from empirically

observed relationships as described by Park, Jones, and Law [29]. The distribution param-

eters were extracted at each time step, and corresponding density histograms (N(r) ) were

derived from them to plot with the experimental data (Figure 2.1-Figure 2.4). The major

parameter in fitting this model to the data is Kit (in units of second-'), and is extracted as

KIL = 1.6xlO exp(-1.O1/kT) 2-15

Physically, this determines the rate at which the interstitials react with the dislocation loop

ensemble. At its high extremity, any concentration of interstitials above the equilibrium

value reacts with the loops, and the reaction is purely diffusion limited. The corresponding

constant for vacancies (KVL) is zero in the simulations.

function for
Park [29]

Initial loop
from TEM


Loss of atoms from
smaller loops.

Gain of atoms for
bigger loops.

Increase in size of
loops with peak-radius

Figure 2.8 Schematic to illustrate implementation of Ostwald ripening phenomenon.

The simulation results match the experimental data for most anneal conditions, indi-

cating that the loop coarsening phenomenon is well modeled. For 7000C minor variations

exist in the height of the histograms for anneals upto 16 hours. However, the total density

(Figure 2.6) of the loops matches the experimental values at this temperature. The simu-

lated and measured bin sizes for the 900C anneal are also in agreement. At 8000C the

model predicts a slightly higher initial dissolution rate of the loops, which results in small

differences in the experimental and simulated bin sizes. Variations in bin sizes for the

experimental and simulated cases diminish if two adjacent bins are added and plotted

together. Such an assumption is valid due to a strong possibility of scatter in the TEM

measurements. This also accounts for the differences in the bin sizes at 10000C, where

large scattering is observed in the experimental data. It should be noted that efforts to

model the initial distribution of loops by an asymmetric distribution function for the 15

min./10000C case lead to some errors which are propagated as the simulation progresses.

However, the simulated total density of the loops is close to what is seen in the experimen-

tal data.

Simulated values for the average radius are plotted along with the experimental val-

ues in Figure 2.5. As seen, the model correctly predicts the average value of the radius for

most anneal conditions.

2.4 Two-Dimensional Growth of Loops Under a Nitride Mask

The kinetics of dislocation loop evolution in ion-implanted silicon are strongly

sensitive to the anneal ambient, which is either inert or oxidizing. It is well known that

oxidation injects interstitials into the silicon substrate. The presence of these extra

interstitials can lead to a sharp increase in dislocation growth rates; in some cases

swamping out the growth due to the Ostwald ripening phenomenon discussed in the

previous section. The growth of loops in an oxidizing ambient was studied in [29]. This

section illustrates a simulation example of combining the two loop growth models into one


Common processing conditions used in semiconductor fabrication involve the use of

a nitride mask. For example, during the growth of isolation oxides, a nitride is used as a

mask for oxidation to prevent the oxide from growing in the active areas. Figure 2.9 illus-

trates the use of a nitride mask in the LOCOS isolation scheme. The loops under the grow-

ing oxide are expected grow at a much faster rate than under the nitride. For the anneal

times considered, the loops under the nitride showed almost no growth in the simulations.

Inert Growth regime Oxidation enhanced

...... *^B


Figure 2.9 Growth of dislocation loops under inert and oxidizing regimes.

As illustrated in Figure 2.9, the loops grow faster under the isolation oxide. Each

node (NI to Nn), is assigned a probability distribution function. The local interstitial con-

centration is considerably larger under the oxide (Figure 2.10). The dip in the plot at the

dislocation loop core is due to the compressive component of the hydrostatic pressure

introduced in the substrate by the loops (Chapter III). This leads to undersaturation of

interstitials in that region.

The two-dimensional model is implemented in Florida Object Oriented Process

Simulator (FLOOPS). The output from the simulator is shown in Figure 2.11.


3.0e+13 -



O.Oe+00 -

0.5 1.0
Depth (um)

Figure 2.10 Interstitial concentration under the growing oxide and the nitride mask. The
excess interstitials under the oxide cause the loops in that region to grow faster.



'( -


x inmicrons



5.0x10 -2






-5.00 0.00 5.00
Figure 2.11 FLOOPS simulation showing the lateral variation of the peak-loop radius
after a 2 hour, 9000C anneal in dry oxygen.

2.5 Summary

A plan view TEM study of the evolution of dislocation loops in silicon during

annealing has been presented. It is shown that with increasing anneal time the average size

of the loops increases while the total density of the distribution decreases. The same

effects are observed with increasing temperature if the anneal time is kept a constant. At


10000C stacking faults are formed beyond 2 hours of annealing. The loop evolution is

shown to follow the Ostwald ripening phenomenon with the large loops growing at the

expense of smaller ones.

A point defect based model which physically accounts for loop-to-loop interactions

is developed from Park, Jones, and Law's [29] model. It correctly predicts the evolution of

loops for most anneal conditions. Constants which define the rate of reaction between the

loops and point defects are extracted for the 700-10000C temperature range.


Type-II end of range dislocation loops are formed under common implant and

anneal conditions used in ULSI circuit fabrication. They affect dopant redistribution and

can subsequently alter the electrical properties of the device. To design devices for optimal

performance, it is important to predict the interaction between dopant atoms and disloca-

tion loops. It has been proposed that the strain associated with these loops is the driving

force for dopant diffusion during annealing [38-40]. An understanding about the source

and magnitude of this strain is essential for process engineers designing devices for opti-

mum performance. The loop strain is found to be a strong function of dislocation loop size

and density, which changes during the anneal [41, 42]. A comprehensive model should

take into account both the evolution of the loops and the strain. Such a model would be a

useful tool for the device technologist.

In the past, Transmission Electron microscopy (TEM) has been used to characterize

the evolution of extended defects under a wide range of anneal conditions [29, Chapter II].

While TEM can give adequate information about loop evolution, it does not provide any

direct information on the strain fields associated with these defects. Recently, the tech-

nique of High Resolution X-Ray Diffractrometry (HRXRD) has been developed for the

analysis of strain in ion-implanted semiconductors [41-43]. It allows for the strain and

defect analysis to be performed on the same sample.

Figure 3.1 A matrix of the samples prepared and analyzed in this study.

In this study, a comprehensive two-dimensional numerical method is developed to

model loop evolution (verified by the TEM data), and the resultant strain (verified using

the HRXRD data). Additionally, the model predicts stress versus depth profiles in the sub-

strate, not available from the x-ray analysis.

3.1 Experimental Details

The experimental procedure was designed and executed by Thompson [41]. The

experiments were conducted using <100> Czochralski grown silicon wafers. These wafers

were p-type (boron doped) with a resistivity of 5-10 02-cm, a diameter of 76 mm, and a

thickness of 356-406 tm.The wafers were implanted with Ix 1015 28Si+ /cm2 at an energy

of 50 keV using a Varian ion-implanter. The ion beam was kept at a minimal current to

reduce possible heating of the sample. After implantation a 5500 A SiO2 was deposited on

the wafer to prevent any oxidation during the annealing process. The wafers were cleaved

into approximately 1 cm2 pieces for annealing and subsequent x-ray analysis. The samples

were annealed in a N2 ambient at 7000C, 8000C, 9000C, and 10000C for times varying

from 15 minutes to 16 hours. The annealing conditions are outlined in Figure 3.1. After

the anneal, the surface oxide was removed from all samples using a buffered oxide etch for

5 minutes. The samples were tested for the presence of any residual oxide, which might

effect the intensity of the x-ray peaks and/or introduce strain in the sample.

The fundamental result from the HRXRD is a rocking curve. A rocking curve is an

angular x-ray scan around the Bragg diffraction-spot of a particular crystallographic plane.

It plots the diffracted intensity around the Bragg angle; the collected intensity being lim-

ited by the geometry of the system. For most systems, the "rocking" is performed by mov-

ing the sample through the Bragg angle. If a layer of different lattice parameter is present,

either on the surface or underneath it, two peaks will be evident in the rocking curve. One

peak represents the substrate while the other peak indicates the presence of the strained

layer. The separation between these peaks provides the difference in lattice parameter

between the layer and the substrate. From a combination of different scans and from TEM

data, the strain and/or relaxation in the system can be determined. Further details about the

x-ray analysis are available in Thompson [41].

3.2 Experimental Results

The loop evolution, in an inert ambient, is observed using TEM microphotographs.

The average loop radius is measured for each anneal condition, and is plotted as a function

of the anneal time and temperature in Figure 3.2. It increases with anneal time, though the

growth rate is small at low temperatures. It is also apparent that for a fixed anneal time the

average loop radius is greater for the higher temperature anneals. The loops are quite small

during the early stage of the 7000C anneal. The increase in the average radius of the loops

above 8000C is associated with Ostwald ripening of the loops. This process was discussed

and modeled in Chapter II.

The change in the total loop density, as a function of the anneal conditions, is shown

in Figure 3.3. A decrease in the density is observed with increasing anneal time for most

cases. If the time is kept constant, the density is found to decrease with an increase in tem-

perature. This is the result of the loop coarsening process, during which the larger loops

grow at the expense of smaller ones, which eventually dissolve. For the 7000C anneal the

density remains fairly constant during the first two hours of the anneal.

The sharp drop in the number of trapped interstitials in the first two hours of the

10000C anneal indicates that the loops are in a dissolution regime at this temperature. For

the 8000C and 9000C anneals, the loops remain in the coarsening regime and the densities

of interstitials bound by the loops remain almost constant (Figure 3.4).

The peak strain in the silicon lattice, from both the experiments and simulations

(Section 3.3), is plotted in Figure 3.5. The change in the magnitude of this strain with time

is minimal for the lower temperature anneals. However, at higher temperatures (10000C)

there is a sharp drop in its magnitude during the first two hours of the anneal. It appears

that the magnitude of the strain is sensitive only to the anneal temperature for temperatures

below 9000C. However, at elevated temperatures (> 9000C), it is a strong function of both

the time and temperature of the anneal.

400.0 I I I

300.0 1000oC

0 200.0 -
> 9000
100.0 80o0C
0.0 300.0 600.0 900.0
Time (minutes)

Figure 3.2 Experimental (filled) and simulated (empty) size of the average loop radius
for various anneal conditions. At low temperatures the loops are small and the growth
rate is not very pronounced. At higher temperatures, the small loops dissolve and the
freed interstitials aid in the growth of the larger loops.

1012 I I

S10 800C

9 9000C
Q 1010 o
0 10000C

109 ,- I -
0.0 300.0 600.0 900.0
Time (minutes).

Figure 3.3 Experimental (filled) and simulated (empty) values of the total density of
loops for various anneal conditions. The sharp drop in the density for the 10000C anneal
is representative of the loop dissolution process. Coarsening of loops is evident for the
800-9000C anneals.

, 1015


< 1014

Time (minutes)

Figure 3.4 Experimental (filled) and simulated (empty) values of the captured interstitial
dose for various anneals. The implantation induced interstitials coalesce to form disloca-
tion loops and are responsible for the strain in the crystal.






300.0 600.0
Time (minutes)


Figure 3.5 Experimental (filled) and simulated (empty) values of peak strain for various
anneals. The dissolution of loops for the 10000C anneal clearly reflects itself in the sharp
drop in the strain at that temperature.


l7000C 9000C (Exp.)

I ZJ 800C

on 90/0C (Sim.)

3.3 Modeling

As observed in the experimental data, the strain and the dislocation distribution in

the silicon lattice are strongly coupled. This implies that a predictive model should incor-

porate this coupling. In this approach, loop evolution, as observed in the TEM micropho-

tographs, is simulated using the Ostwald ripening models discussed in Chapter II. A

model for strain, based on the number of atoms trapped by the loop ensemble, is devel-

oped and used at each time step of the simulation as an input to the Ostwald ripening

model. A flow schematic of the modeling methodology is shown in Figure 3.6, and illus-

trates the coupling between the strain and loop distribution properties.

Figure 3.6 Block schematic for model implementation in FLOOPS. The box in the mid-
dle represents the Ostwald ripening model described in Chapter II.

3.3.1 Modeling Loop Evolution from TEM Data

A model to predict the evolution of loops in an inert ambient was developed in

Chapter II. Numerically calculated values of pressure are used in simulations for this

work. Loop evolution is indirectly influenced by the presence of the loop ensemble,

because of the pressure field it creates. The presence of a compressive field, for example,

leads to an undersaturation of interstitials, thereby affecting the local concentration of

point defects around the loops. Figure 3.7 illustrates the effect of a pressure field, from an

ensemble of dislocation loops, on an impurity atom or point defect.

Figure 3.7 Interaction between the pressure field from a dislocation layer and a point
defect in its vicinity; ro is the measure of the sphericity of the defect and e is the dilata-
tion which determines the elastic inclusion of the defect.

The interaction between the loops and the point defects described in the preceding

paragraph is mathematically governed by the following equations:

C,*(P) = C *(P = O)exp kTJ 3-1

Cy*(P) = Cv*(P = O)exp ---k 3-2

where C1/v* (P) is concentration of interstitials in the presence of the pressure field, P is

the spatially dependent magnitude of the pressure field, k is the Boltzman's constant, and

T is the temperature. AV, and AVv are effective interstitial and vacancy expansion vol-

umes, and are defined as

AV, = 1.33K1Er3 3-3

AVV = 27rr2YF/4 3-4

where ro and E are defined in Figure 3.7, rs and F are the radius and surface tension of

the vacancy well respectively, gt is the shear modulus of silicon, and y is related to the

Poisson's ratio ri of the material (= 0.3 for silicon) as

y = 3.0 1-O 3-5
1+ T

The value of used in the simulations is 0.5, which is reasonable in its meaningful range

(0 < <1).

3.3.2 Modeling the Strain from HRXRD Data

Park et al. [29] developed an analytical model for pressure from an ensemble of dis-

location loops by summing the pressure contributions from individual loops. The model

was limited to cases where the peak radius Rp was smaller than inter-loop distance LALL,

i.e., the case in which the loops did not overlap. The simulation was also restricted by loop

morphology and location. Pressure profiling in two-dimensions, for example under

masked and unmasked regions, was not possible.

Extra Atoms due to the loops

R -min _


Figure 3.8 A plot of the extra number of atoms in the lattice due to the loops as a function
of depth in the lattice.

A new numerical model based on the strain from the extra number of atoms in the

lattice is developed in this section. It allows the loops to grow indefinitely till they overlap.

It can be extended for simulating pressure from elliptical or other geometrically shaped

loops. The two-dimensional extension of the model allows pressure values to be computed

in masked and unmasked sections separately, and is the discussed as part of the next sec-


The strain from an ensemble of dislocation loops can be thought of as the change in

the lattice parameter the loops produce in the lattice. Thus, the number of extra atoms due

to the loops should be a good indicator of the strain in the lattice. For a given dislocation-

loop density this number increases as the core of the dislocation loop ensemble is

approached, since more loops contribute to the number of extra atoms in the lattice. Thus,

the peak strain in the lattice is expected to be near the core of the loops, as shown in Figure


A mathematical expression for the plot in the Figure 3.8 is formulated as follows:

the number of interstitials due to loops of radius R, and density D(R) is given as

tR2 DIIo-D(R) = 4-Dlio.D(R).J( R2-X2.dX) 3-6

where D110 is the density of silicon atoms in the <110> plane and X is the distance from

the center of the loops as shown in Figure 3.8. If N(XR) is the depth dependent number

of atoms due to loops of radius R, it follows:

J N(XR)dX = 2* JN(XR)dX = 4 D -D(R)* jf 2 -2 dX)
-R 0 0

Thus the number of atoms trapped in the loops of radius R is

R2 2
N(XR) = 2 D(R) D110- R X

which for all the loops is NALL(X), given by

NALL(X) = N(X) = 2 10

J fD(R) R2-X2dX

Notice that the lower limit in the integral of Equation 3-9 is X because loops of

radius less than X do not contribute atoms at that depth.

A finite element method is used to solve for the stress in the entire structure, using

the quantity in Equation 3-9 to specify the normal component of the initial strain Co

Exxo = NALL(X)/5.02xlO22


where the second quantity on the right hand side is the density of silicon atoms in the lat-

tice. This can be converted to an initial strain force fm for a volume V:

fm = BT D FodV 3-11

where D and B are the elasticity and strain-displacement matrix, respectively. This is

used in the balance of forces equation described in Zienkiewicz and Taylor [44]. Nodal

displacements are solved for and converted to stresses. The peak pressure in the structure

is then obtained and divided by the bulk modulus, to obtain the peak strain. A plot of pres-

sure in the lattice with increasing depth is drawn in Figure 3.9. The pressure peaks at the

dislocation loop-core and decreases rapidly away from it.

4.5e+09 ,

F- 3.5e+09
D 2.5e+09

Dislocation loop corr

QL 5.0e+08

-5 .0e+08 i i
-0.0 0.10 0.20 0.30 0.40 0.50
Depth (gtm)

Figure 3.9 A plot of the simulated pressure in the substrate due to the loops. The com-
pressive pressure peaks at the core of the dislocation loops. The absence of tensile stress
at the edge of the loop layer is due to the displacement boundary condition used. This is
further discussed in Section 3.3.3.


L E (b)

Figure 3.10 Boundary condition for normal displacement: (a) reflecting, (b) periodic,
and (c) laterally restricted.


4.0e+09 I-

2.0e+09 I

0.0e+00 (

-2.0e+09 '





Depth (p.m)

Figure 3.11 The effect of the lateral boundary conditions on the pressure around the dis-
location loops. The effect of the boundary condition on the tension at the border of the
loop layers is pronounced. However, the spread of the compressive pressure and its mag-
nitude agree for all the boundary conditions studied.

G-o Reflecting
E-a Periodic
o---c Laterally Rest.
A-A Analytical





--------- ------


3.3.3 The Effect of Boundary Condition

The magnitude of the tension at the loop boundaries is a strong function of the

boundary conditions used in the simulations. The plot in Figure 3.9 is for a reflecting

boundary condition where the normal component of the displacement is forced to be zero

at the structure boundaries. This boundary condition is depicted in Figure 3.10 (a). The

lateral edges, in this case, can be thought of as mirrors. The intended effect is to simulate

the loops extending infinitely in both the lateral directions. Such a boundary condition is

commonly used in mechanical and thermal problems to minimize the number of gird

points, by simulating a unit cell of the periodic structure. The compressive pressure (Fig-

ure 3.11) predicted is close to the results from using the other boundary conditions. How-

ever, not allowing the lateral edges to move laterally forces the tension at the loop layer

edges to be close to zero. The effect can be better understood by considering an elastic

string that is pulled in one direction. It experiences a shrinkage in a direction perpendicu-

lar to the force. Likewise, the loops exert a compressive force in a direction perpendicular

to the surface of the structure. This tends to push the lateral edges outwards. By preventing

the edges from moving the boundary condition artificially induces a small compression

which swamps out any tension existing at the loop boundaries. It is evident that to simu-

late this tension correctly some other approach is needed.

Cifeuntes and Stiffler [45, 46] used another approach to simulate periodic cells by

using the "periodic" boundary condition. In this approach, depicted in Figure 3.10 (b), one

of the lateral edges (the left one in this case), is used as the mirror, by forcing the normal

component of the displacement to be zero along it. However, the other lateral edge is

allowed to move by a constant distance. For the model implemented in FLOOPS, all the

nodes along this edge are mapped on to the topmost node of the edge. Thus, all the nodes

along the right edge are restricted to the same value of the normal displacement. If the cen-

ter of the structure now lies on the left edge, the simulation mimics an infinitely extending

loop layer. The main advantage of this approach is that it allows motion along the right

edge. Some tension at the loop boundaries is observed (Figure 3.11), though the magni-

tude is smaller than the case of "laterally restricted" boundary condition which is dis-

cussed in the next paragraph.

The last set of boundary conditions investigated is the "laterally restricted" case.

Simulations for a single loop reveal that pressure from it reduces to insignificant magni-

tudes at distances greater than twice the minimum inter-loop distance defined in Equation

3-13. Thus, the validity of this boundary condition arises from the fact that dislocation

loops far away (laterally) from the regions of interest do not influence the magnitude of

pressure. The loops are initialized for a lateral distance y defined as

-2LALL < y < 2LALL 3-12

LALL= 3-13

where DALL is the total density of all the loops. The boundary condition is illustrated in

Figure 3.10 (c); the width of the shaded dislocation region is defined by Equation 3-12.

The displacement at the lateral edges of the loop layers is now free and enhanced tension

is observed at the loop layer boundaries. However, the magnitude of this tensile pressure is

less than the analytical solution of Park, Jones, and Law [29].

3.4 Data Analysis

An analysis of Figure 3.5 shows that the strain decreases with increase in tempera-

ture. For temperatures below 10000C, the loop density, number of captured interstitials,

and strain do not change much with increasing anneal times. The average loop radius

increases with anneal time, and is consistent with earlier work [Chapter II, 47, 48]. This

section correlates the characteristics of the loop ensemble with the peak strain.

3.4.1 Correlation of Peak Strain with Captured Interstitials

For the 7000C, 8000C and 9000C anneals, no pronounced variation in the number of

captured interstitials with anneal time is observed (Figure 3.4). This is reflected in the

strain plots of Figure 3.5. The simulated values of the captured interstitials are higher in

most cases, implying that some interstitials are being lost to the lattice. The model does

not account for the strain from these "lost" interstitials. Since the strain from a free inter-

stitial is expected to be higher than from an interstitial in a loop, the simulated values of

strain are lower than the experimental values. However, this difference is not large for

most anneal conditions. It is plausible that the interstitials released by the loops quickly

diffuse away from the regions of high strain. Not accounting for the strain from them does

not effect the accuracy of the simulations. For 10000C anneal, the loops dissolve and the

number of captured interstitials goes down rapidly. This causes the strain to fall sharply,

and is seen in both the experimental and simulated data.

3.4.2 Correlation of Peak Strain with Loop Density and Radius

The loop density does not vary much at lower temperatures. However, at higher tem-

peratures it begins to decrease with increase in anneal times. For the 800-9000C tempera-

ture range the loop coarsening phenomenon is evident as the smaller loops dissolve and

the larger loops grow. At higher temperatures, loops of all sizes dissolve, though their

simultaneous coarsening is seen in Figure 3.3. The strain seems to have a similar trend,

decreasing sharply at higher temperatures, and remaining almost flat for the lower temper-

ature anneals.

Though it is clear that the loop radius increases with increasing anneal times, it is

not readily apparent how the peak strain is related to the average loop radius. The average

loop radius, which is an indicator of how large the loops are could be important in relating

the spread of the strain in the lattice. The larger the loops, the larger the length of the

strained lattice. Such information is available from simulations, but has not been verified

by any experimental data (Figure 3.9).

3.5 Pressure Profiling for Two-Dimensional Structures

Section 2.4 discussed the implementation of a two-dimensional model for disloca-

tion loop evolution. Simulations revealed the growth rate under the growing oxide was

much larger than under the inert nitride due to the presence of the oxide injected intersti-

tials. As part of a purely simulation effort, the effect of loop growth on the resultant pres-

sure profiles is studied. It is assumed that the effect of the growing oxide on the substrate

below is limited to the injection of interstitials and stress effects from it (which can be sub-

stantial for non-planar oxidation) are negligible.









-8e+08 I I I I
0.07 0.12 0.17 0.22 0.27
Depth (gjm)
Figure 3.12 Pressure plots for dislocation loops annealed under an oxide and nitride for
60 minutes. The peak compressive pressure, and the spread, are larger for the loops
growing under the oxide, where the injected interstitials contribute to faster loop growth.

As seen in Figure 3.12, the compressive pressure for the larger loops under the oxide

is greater. The spread of this compressive pressure is also larger for the loops grown under

the oxide. The reflecting boundary condition is used for the simulations.

3.6 Summary

A two-dimensional finite element model for strain from trapped interstitials is devel-

oped. Loop evolution is modeled using the Ostwald ripening phenomenon. Strain from

free interstitials is not modeled in the study, and could account for differences in the simu-

lated and measured values of strain. The model correctly predicts loop evolution in the

inert ambient. The model underestimates the strain for long anneals in the 800-9000C

range. Coupling of the strain to the local point defect concentrations is also implemented.

Though not verified by experimental data, the pressure distribution in the lattice due to the

loops is simulated.


Modem integrated circuit processing relies on the use of thin films for a myriad of

purposes. Polysilicon films are used for contacts and short interconnects. Silicon dioxide

films are either thermally grown (gate oxides in MOSFETS), or deposited by various

Chemical Vapor Deposition (CVD) techniques. The latter category of oxides are fre-

quently used as dielectrics between the various levels of metallization. Silicon nitride films

are also frequently used in silicon processing. The self-limited thermal growth of these

films leads to a reproducible process, since variables such as growth pressure, tempera-

ture, and time have a weak influence on the eventual film thickness. An important use of

nitride films is as oxidation resistant masks in device isolation schemes, where oxides are

selectively grown on recessed/semi-recessed substrates.Their high density enables nitrides

to be frequently used as diffusion masks, in preference to silicon dioxide or silicon oxy-

nitride films. On account of their high dielectric constants, nitrides are also used as dielec-

tric barriers in silicon technology. Epitaxial layers have become very common in modem

technology. In MOSFETs they are used to improve the latchup resistance. They are also

useful in reducing alpha-particle induced soft errors in memory devices.

The use of thin films in silicon technology is accompanied by stress in the thin films

themselves and in the silicon substrate below. Films like silicon nitride, CVD oxide, etc.,

have elastic stress present in them as an inherent part of the deposition process. This stress

can either be tensile or compressive, the sign and magnitude being strongly dependent on

the processing parameters, viz., substrate temperature, type of substrate, rate and method

of deposition. The sign of the stress in the film can easily be determined by looking at the

shape of the film-substrate composite structure, as illustrated in Figure 4.1. A convex cur-

vature results when the relaxed film is forced to fit (compressed) onto a substrate of shorter

length (Figure 4.1 (a)). In this case the film is in compression, while the substrate immedi-

ately below it is in tension. However, if the film needs to be stretched to fit on the sub-

strate, it experiences a tensile force, and the substrate below it is in compression (Figure

4.1 (b)).

(a) Compressive Stress


(b) Tensile Stress

Figure 4.1 Thin film stress; (a) convex curvature indicates a compressive stress in the
film, while (b) concave curvature represents a tensile stress in the film.

Thin film stress can be subdivided into two major components. The thermal compo-

nent ath arises due to the difference in the thermal expansion components of the film and

the substrate, and is given as

th = YF(F- cs)AT 4-1

where YF is the Young's modulus of the film, aoF and as are the thermal expansion coef-

ficients of the film and substrate, respectively, and AT is the film deposition or growth

temperature minus the temperature at which the stress is measured. The intrinsic stress of

the film is more complex and less understood. It is a strong function of film deposition

conditions such as temperature, pressure, and gas flow rates. Changes in film deposition

parameters may change the magnitude or even the sign of the resultant stress in the film.

A convenient way to analytically calculate the stress in a thin film is to measure the

magnitude of wafer bending (d in Figure 4.1 (a)) caused by the deposition or growth of

the film. If Ys and YF are the Young's modulus of the silicon substrate and film, respec-

tively, ts and tF the thickness of the substrate and film, respectively, L is the length of the

substrate, and gi is its Poisson's ratio, the film stress is given from plate bending theory

[49] as

dYsts ( Y t4-
F = I 1+--. F 4-2
3L2 F(1 ) YS s

which for a very thin film reduces to

SYsts 4-3
F 6rtF(1 p)

where r (=L 2/2d), is the curvature of the bent substrate.

High values of stress from thin films can detrimentally affect the operation of

devices. For example, a compressive stress in the substrate can retard the diffusion of

boron [50, 51]. If the film is not continuous or is non-planar significant stress is generated

in the substrate [52, 53], which might then yield to form dislocations. Analytical models

like those given in Equations 4-2 and 4-3 suffice for simpler geometry. For complex

shapes frequently encountered in modern device processing, a more robust technique with

a correct set of boundary conditions is needed. This chapter attempts to model stress

effects in silicon due to nitride stripes and epitaxial growth. The finite element code in

FLOOPS is used to numerically simulate stress in the silicon substrate. The use of proper

boundary conditions to simulate periodic structures commonly found in ULSI technology

is investigated.

4.1 Stress from Nitride Stripes

Nitrides are often patterned on the silicon substrates as isolation masks or as diffu-

sion barriers. For structures like memory circuits equidistant nitride stripes are patterned

on the silicon substrate. If these stripes are very wide, the stress in the substrate is not very

pronounced and does not affect the device operation. However, if the stripes are narrow,

high levels of stress are generated around the nitride mask edges.

4.1.1 Implementation in Finite Element Code

The finite element code is a robust method to calculate stress from a variety of

sources. The finite element code in FLOOPS is used to simulate the effect of intrinsic

stress in nitride films on the substrate, by specifying the lateral component of the initial

strain Eyyo. This can be converted to an initial strain force fm for a volume V in the

nitride as

fm = BT D F-odV 4-4

where D and B are the elasticity and strain-displacement matrix respectively. This is used

in solving the balance of forces equation [44]. Nodal displacements are solved for and

converted to stresses. The viscoelastic code in FLOOPS is used in its elastic limit by spec-

ifying a large (~ lxl020 Po.) number for the viscosity for both the nitride and silicon.

4.1.2 A Single Nitride Stripe

Figure 4.2 illustrates the displacement vectors due to a single nitride stripe, 5

microns wide and 200 A thick. The lateral edges are not constrained and are free to move

vertically. The substrate is 5 p.m thick and its bottom edge is constrained from moving

downwards; though lateral motion is allowed. This set of boundary conditions corresponds

to an isolated nitride stripe-silicon substrate composite structure. The displacement vec-

tors in the plot can now be analyzed from first order physics. The deposited nitride is

assumed to be under tension. If the stripe extends over the entire substrate, a compressive

stress, 2-3 orders of magnitude less than in the nitride would exist in the substrate below.

This is because the substrate is 2-3 orders of magnitude thicker than the nitride. However,

if the nitride is patterned, as is the case for the simulation in discussion, the edge effects

cause a large stress to be generated in regions close to the edge. The tension in the nitride

causes a "lift-off" effect in the region to the left, causing it to go into tension. The region

immediately below the nitride is pushed down and is in compression. A pressure plot from

left to right illustrating this above behavior is illustrated in Figure 4.3.

4.1.3 Stress from Multiple Nitride Stripes

Periodic structures consisting of identical unit cells are common to many semicon-

ductor devices like memory chips. Thus, a pattern of nitride stripes of equal width and

spacing are commonly found during ULSI processing. If the stripes are sufficiently close

to each other, as is the case for scaled devices, the isolated behavior discussed in the previ-

ous section ceases to be valid. Stress from neighboring stripes can effect the local pressure

values. This section looks at the effect of multiple nitride stripes on the net pressure in the

substrate below. A large number of stripes are initially simulated and then their number

reduced till there is no loss of accuracy. It was observed that a minimum of three stripes

are necessary to mimic the periodicity of the entire structure.

4 J ~J ,~ ,~1/ii

J J ,~ ) ~


~ i~ ) 33~Ii

~ \~ \~ ~j















33 33 3

3, ~

-4.00 -2.00 0.00 2.00 4.00

Figure 4.2 Displacement vectors due to intrinsic stress in a single nitride stripe. The lat-
eral edges are allowed to move vertically. The tensile stress in the nitride tends to pull the
silicon substrate up at the left side (in tension), and push down the region immediately
below it (in compression), as is seen by the displacement vectors. A plot for the actual
stress in the substrate is shown in Figure 4.3.

31 31
1 ~
33 I

~ ~ ) .~
'~ ~






-1.0e+08 -

-3.0 -1.0 1.0 3.0


Lateral distance (gm)

Figure 4.3 Pressure plot for a lateral cut (x=0.2 microns) through the structure shown in
Figure 4.2. The stress changes from tension to compression from left (bare) to right (cov-
ered with nitride). The intrinsic tension in the nitride film is 1.4el0 dynes/cm2.

The structure in Figure 4.4 shows multiple nitride stripes, 5 microns wide and apart,

and 200 A thick, patterned on the silicon substrate. The effect of the neighboring stripe on



the local values of stress is evident from the plot. The tension at the left edge of a single

cell is enhanced, while under the nitride the compressive forces are reduced. This is to be

expected, as the adjacent stripes on both the left and right of the unit cell add to the ten-

sion, increasing the tensile forces on the left and decreasing the compressive forces below

the nitride. The stress in the silicon substrate is a strong function of the stripe thickness

and width. This dependence is discussed throughout this chapter.

The principle slip pattern in silicon for the <111> plane is the <110> direction. This

corresponds to the force due to the shear stress component. A value of 3x107 dynes/cm2

has been reported by Hu [12] to be the critical shear stress for slip in silicon. Dislocations

in regions having a shear stress component greater than this value will move. The shear

stress contours for the nitride stripes under discussion are shown in Figure 4.5. The con-

tour is a double lobe because the shear stress is related to the polar coordinates as

az = (ar-( e)sin20 + rocos20 =arsin26 4-5

the function sin20 peaking at 45 degrees from the vertical edge. The plot indicates that a

dislocation moving under the influence of the stress field will continue to do so till it

passes under the mask edge, where it might get stranded as the shear stress value may fall

below the critical value for slip. The plot also shows that the nitride film's influence, as

regards the shear component, extends about 1 micron deep and 2 horizontally from the

edge. This could be significant in scaled ULSI structures. A behavior similar to this was

presented in Figure 1.6.

Stripes 2i







Silicon Substrate


Multiple Stripes
0--O0 Single Stripe



J. .1

-17.5 -7.5 2.5 12.5
Lateral Distance (gim)

Figure 4.4 Multiple nitride stripes used to simulate pressure contours. The plot depicts the
effect of neighboring stripes on the local stress.

















f i E



I ~I j
Ii I I
it II
1 1

a ; VWArfMf

-10.00 -5.00 0.00
Figure 4.5 Shear stress contours (for -3x 107dynes/cm2) due to intrinsic stress in a depos-
ited nitride stripe. The lobes peak at 45 degrees and represent critical values for disloca-
tion loop glide.

4.1.4 Stripe Width Dependence of Stress from Multiple Stripes

As the nitride stripes are made smaller and brought closer together a greater interac-
tion between them is expected. The hydrostatic component of the stress (i.e. pressure), as
well as the shear component follow the laws of algebraic superposition, where the stress at

a point is the linear sum of the stress from all the stripes in the structure. A plot of the pres-

sure for different nitride stripe widths is shown in Figure 4.6. The thickness of the nitride

film is kept constant at 0.1 pgm in the simulations. In the regions immediately below the

film/substrate interface an increase in the peak values of both the compression and tension

is observed with decreasing stripe width and spacing. The compressive pressure peak due

to the 2.5 gpm stripe is almost three times that of the 10 p.m stripe and the trend would con-

tinue for smaller stripe widths.

8.0e+08 I *

0 2.5 Im
E 6.0e+08 A A 10.0 gm


a 4.0e+08 -

T- 2.0e+08 -

0.0 1.0 2.0 3.0 4.0
Depth (gm)

Figure 4.6 Plots of pressure, as a function of depth in the silicon substrate, in the middle
of the stripe, for various stripe widths, and a nitride film thickness of 0.1 pm. As the
stripes get smaller and closer, the compressive and tensile pressure peaks get bigger in
magnitude, indicating the effect of the neighboring stripes. However deeper in the sub-
strate stress from the wider stripes is higher.

A completely different scenario exists if we look at the stress levels deeper in the

substrate. At roughly about 1.5 microns the stress from the 10 gim stripes becomes greater

than the 1 p.m wide stripes. This is because stress due to the smaller stripes falls off rap-

idly, while it extends deeper into the substrate for the wider stripes.

4.1.5 Shear Stress in Substrate from Multiple Nitride Stripes

The effect of multiple nitride stripes on the shear component of the stress is mark-

edly different. This section examines the stripe width and thickness dependence of the

shear stress in the silicon substrate.

0.00 .-Regions

0.20 --3.0x107
/ )- --3.0x107

-2.00 -1.00 0.00 1.00 2.00
Figure 4.7 Shear stress contours for the critical value of dislocation glide (~3x 107dynes/
cm 2) for varying stripe widths.


1 e+9



le+9 -



0.0 5.0

10.0 -10.0


-10.0 0.0 10.0 20.0
Stripe Width (g n)

10.0 20.0


Figure 4.8 Lateral variation in shear stress, at a depth of 0.1 gpm for varying stripe widths
for a 0.2 gim thick nitride stripe. The peaks at the edges of the stripe begin to overlap as
the stripes are brought closer together.

As the stripes are bought closer together, the shear stress components tend to offset

each other; the tensile component from the one stripe offsets the compressive component

of the adjacent stripe. The effect is illustrated, for decreasing stripe widths, in Figure 4.7.

The lobes for the 2.5 gm stripe are the smallest, and the region of dislocation glide is


roughly half that of the 10 pm stripes. Thus, as the stripes are brought closer together, the

hydrostatic component of stress add up while the shear components offset one another in

regions immediately below the nitride-silicon interface.

The contours in Figure 4.7 indicate that the shear stress peaks near the edge of the

patterned film. Since the shear component of stress has implications on bulk processing

(e.g. dislocation loop glide and substrate yielding), it is useful to investigate its lateral vari-

ation under the patterned film. Results of the simulations are plotted in Figure 4.8 for a 0.2

p.m thick nitride stripe. The stripe widths range from 2.5 gpm to 10 pJm. The plots are at a

depth of 0.1 pim below the nitride silicon interface. For the case of the widest stripes the

shear stress "peaks" are smaller in magnitude and reduce to almost zero in the middle of

the stripe. However, as the stripes are made smaller and brought closer together the peaks

begin to overlap in the middle of the stripes.

4.1.6 Film Thickness Dependence of Stress from Multiple Stripes

The use of a nitride layer as a diffusion or oxidizing mask is often limited by its

thickness. It would be interesting to look at the effect of nitride stripe thickness on the

stress in the substrate below. A first order analysis makes it obvious that a thicker nitride

would result in larger numbers for stress in the substrate below. The simulations not only

reveal results in accordance with this analysis, but also suggest that the ratio of the film

thickness to its width is important in determining the shape of the pressure plot in the sub-

strate immediately below the middle of the stripe.

2.0e+09 i

---e 2.5 gm
E 1.5e+09 A A 10.0 pm

*o 1.0e+09 -

.) 5.0e+08

0.Oe+00 -
0.0 1.0 2.0 3.0 4.0
Depth (gm)
Figure 4.9 Pressure plots in the middle of the stripe for various stripe widths for a nitride
film thickness of 2 pm. As the stripes get smaller and closer (in contrast to Figure 4.6),
the compressive pressure gets smaller in magnitude.

The "stripe width" dependent behavior discussed in section 4.1.4 remains valid as

long as the thickness of the nitride film is small compared to its width. However, if the

thickness of the film is increased and becomes comparable with the width of the stripe, the

"stripe width" dependence of the stress in the substrate below markedly changes. The

average hydrostatic pressure (stress) now decreases with shrinking stripe width, in contrast

to the results of the previous section (Figure 4.9). The simulation is for is for a 2pm thick

nitride stripe for stripe widths ranging from 2.5 to 10 pm. The pressure due to the wider

(10 pm) stripe is now larger, when compared to the smaller (2.5 pm) stripe. As in the case

of the thinner film, the stress from the wider film extends deeper into the substrate, while it

falls rapidly for the smaller stripe.

2.0e+09 .vp" k

E 0.Oe+00

-2.0e+09 -

-4.0e+09 0.1 gm ^,
........ 1.0 m
v 7 L2.0 pm

-6.0e+09 '
-20.0 -10.0 0.0 10.0 20.0 30.0
Lateral Position (rnm)
Figure 4.10 Film thickness dependence of the pressure in the silicon substrate for the
case of 10 gim wide stripes at a depth of 0.1 gim. The pressure increases as the thickness
of the film is increased. Also, the shape of the plot changes from convex to concave at a
thickness of approximately 1.25 jm.

It is also interesting to observe the effect of increasing film thickness on the lateral

variation in the hydrostatic pressure. A look at Figure 4.10 indicates that the shape of the

pressure plot in the middle of the stripe is convex for very thin films. However, if the film

thickness is increased ten fold to 1 gim, the pressure variation in the middle of the stripe

changes from convex to an almost flat shape. If the thickness of the film is further

increased to 2 gm, the pressure variation is concave, i.e., the compressive pressure is max-

imum in the middle of the stripe. Therefore, the ratio of the width to the thickness (w/t) is

important in determining the shape and magnitude of the stress in the substrate below. A

quantity, (w/t)crit, can be defined as the ratio of the width to the thickness of the nitride

film for which the lateral variation in pressure in the region immediately below the middle

of the deposited stripe is flat. For the 10 jim stripe width the critical ratio ((w/t)crit) is

found to be ~ 8.

As discussed earlier, the ratio of the width (w) of the stripe to its thickness (t) is

critical in determining the lateral variation of the pressure. Simulations were performed to

investigate the dependence of (w/t)crit as a function of the stripe width. The variation of

the (w/t)crit is found to be perfectly linear with stripe width (Figure 4.11), corresponding

to a slope of 8. This ratio is valid for shallow depths in the substrate (< 0.4 gim). Since

bulk processing is predominantly dependent on stresses in regions at this depth, this ratio

assumes importance. It is valid for all stress levels in the film. If the compressive pressure

immediately below the middle of the stripe is taken as the reference, films with

w/t > 8 4-6

will show a decrease in the pressure with increasing stripe width, and films with

w/t < 8 4-7

will show a increase in pressure with increasing stripe width.

6.0 I

4.0 -


10 1.0

0.0 I I I I
0.0 10.0 20.0 30.0 40.0
Stripe Width (pm)

Figure 4.11 The variation of stripe thickness with stripe width, which results in a flat
pressure profile in the middle of the stripe. The variation is found to linear with a slope of

4.1.7 Film Thickness Dependence of Shear Stress

Widely spaced stripes (10 microns) are chosen to investigate the effect of film thick-

ness on shear stress. Figure 4.12 illustrates the effect of increasing nitride thickness on the

shear stress component in the substrate below. The lobes are poorly formed for the 50 A

nitride. As the thickness of the nitride film is increased the characteristic twin lobes

develop and the area of influence extends deeper and wider in the substrate. It is evident

that an upper limit exists to the nitride thickness that can be used as a mask.


Figure 4.12 Shear stress contours for varying nitride thicknesses. The characteristic
twin lobes barely begin to form for a 50A thick nitride, but are well developed and much
deeper for thicker nitrides. The jagged edges in some of contours are grid related and not
a real effect.

4.2 Wafer Curvature Due to Lattice Mismatch

The use of epitaxial films, where single crystal silicon is grown on top of the silicon

substrates, is a standard feature of many ULSI processes. Epitaxial p/p+ structures are

frequently used to improve latchup susceptibility in CMOS devices and to reduce the

frequency of alpha-particle induced soft errors in memory devices. An artifact of the

epitaxial process is the lattice mismatch that results from the difference in dopant

concentrations in the substrate and the epitaxial layer. The heavily doped side, i.e. the

substrate, is relaxed from the melt process. However, the growth of the lightly doped

epitaxial layer causes an interfacial mismatch of the lattice parameter. This mismatch is

directly proportional to the difference in the dopant concentrations.

Depending on the level of the mismatch the epitaxial-substrate composite reacts in

two ways. If the mismatch is below a critical value, the system relaxes by bending the sub-

strate. If the strain due to the mismatch exceeds the yield value of the system, misfit dislo-

cations are generated. Wafer bending is not desirable from the lithographic standpoint and

misfit dislocations may affect the yield of the process.

Lin et al. [26] investigated the effect of lattice mismatch on wafer bow. They

reported the wafer bow was directly proportional to the level of the interfacial doping mis-

match and the thickness of the epitaxial layer. They also reported the successful use of a

technique called "compensation," which reduced the magnitude of this interfacial mis-


This section develops models for wafer bow and the resultant stress in the silicon

substrate and the epitaxial layer. It is assumed that the epi-substrate composite has not

yielded to form dislocations. However, stress levels predicted by the simulations could be

used to predict the regions along the epi-substrate interface where dislocation are most

likely to form. Additionally, the technique of "compensation" is simulated and the model

is verified from the data in Lin et al. [26].

Center point
kept fixed

Figure 4.13 Diagram illustrating the boundary condition for displacement in the finite
element code used to simulate wafer curvature due to the lattice mismatch between a
heavily doped substrate and a lightly doped epitaxial layers.

It is well known that doping with boron causes the silicon substrate to contract (~

0.014 A/at. % boron). A relation between the substrate boron doping CB and the initial

lateral strain Eyyo that results in the epitaxial layer is given as

0.014 CB 4-8
YYO-- Xx 100l 4-8
YYO X L 22
s 5x10

where Ls is the lattice constant of undoped silicon. This is converted to an initial strain

force for the finite element code by Equation 4-4. The boundary condition used for the

analysis is depicted in Figure 4.13. The lateral edges are left free to move either vertically

downwards and/or laterally sideways. The bottom edge of the structure is also left free

with the exception of one point at the center, which is kept fixed to prevent rigid body

motion. The entire wafer is then simulated and the displacement at the lateral edges are a

direct measure of the wafer bow.

Figure 4.14 depicts the magnitude of the wafer bow for a lightly doped epitaxial

layer and a heavily doped substrate (2x1019/cm3). This results in an interfacial lattice mis-

match of about 5.6x10-4 A. As the thickness of the epitaxial layer is increased the wafer

bow increases.

Figure 4.15 (a) depicts the wafer bow as a function of the interfacial mismatch, rep-

resented as a net strain. The mismatch between the substrate and the epi layer can be

reduced by means of a technique called "compensation" [26]. In this technique the sub-

strate is grown out of a melt consisting of germanium, which acts to increase the lattice

constant of silicon. This compensates the contraction caused by presence of the boron. For

a germanium to boron ratio of 8, complete lattice compensation is measured in the lattice.

This corresponds to the zero strain data point in Figure 4.15 (a). Figure 4.15 (b) depicts the

effect of increasing the epitaxial thickness on the resultant wafer bow, for a constant mis-

match between the epi layer and the silicon substrate.

As shown by the displacement plots in Figure 4.14, the wafer curvature increases

with increasing epi layer thickness, because the thicker epi layer exerts a large stress on

the substrate. If the yield stress of silicon is exceeded then structure will deform by form-

ing interfacial dislocations. Thus, the boron doping in the substrate and the thickness of

the epitaxial layer are limiting factors for dislocation free structures. The use of germa-

nium to compensate the lattice alleviates this problem to some extent. Lin et al. [26]

showed improvement in hold times for memory devices fabricated using the germanium

compensation method.




- 1.OxlO-7




X-Z _Va Plot
X-Z Var Plot
XZVar Plot
XZ Var Plot
ZVar Plot


Increasing Epi Thickness


-5.0x104 0.00 5.0x104 T a. Dis.
Figure 4.14 Displacement plots depicting the extent of the wafer bow for a substrate
boron doping of 2x1019/cm The wafer bow increases with increasing epitaxial thick-


20.0 -

10.0 -

0.0 -






0.0 -

-4.0 -2.0 0.0
Strain x 10"5

5.0 10.0 15.0
Epi-Thickness (gm)

Figure 4.15 The wafer bow as a function of (a) increasing dopant concentration in the
substrate for a 24 pgm thick epi layer, and (b) increasing epi layer thickness.



The macroscopic simulations discussed in this section provide the user with an effi-

cient way of determining the wafer bow for a given epi thickness and substrate doping

conditions. For a given boron doping and epitaxial thickness, stress levels in the epitaxial

film and the silicon substrate can also be simulated. The simulations assume that the sys-

tem has not yielded to form dislocations. Thus, the stress levels given by the simulations

can be used to predict when and where the loops are most likely to form. Additionally, the

model can be used to simulate, and optimize a given process for the technique of "com-


4.3 Summary

Models based on the finite element code in FLOOPS have been developed as part of

this chapter to predict stress in the silicon substrate from patterned and continuous films.

Stress from patterned films was found to be a very strong function of film thickness, stripe

width and intrinsic stress in the deposited film. The stress levels in the silicon substrate

were also found to be sensitive to the depth in the substrate. In general, the stress levels

extended deeper into the substrate for the wide stripes, but fell of rapidly if the stripes

were made smaller and brought closer together. A critical ratio of the film thickness to

length was found to be useful in characterizing the stress levels in the bulk. This work

forms the basis of simulating the experimental data of Chapter V. The simulation results

are described in Chapter VI.

A model was also developed to simulate stress from lattice mismatched epitaxial

film frequently employed in silicon technology. This involved the use of a new boundary


condition in the finite element code, which allowed for both the lateral and vertical defor-

mation in the wafer. The simulated wafer bow was found to be in agreement with the

experimental data. Stress levels simulated using this model could be used in predicting the

onset of misfit dislocations at the epi-silicon interface.


The models developed as part of this work can be broadly classified into three main

categories. In Chapter II, models for the evolution of dislocation loops in an inert ambient

were developed. The simulations were compared with experimental data. Chapter III

investigated stress effects from ion-implanted dislocation loops. The peak value of the

simulated strain was verified from experimental data. Finally, stress from films was the

focus of Chapter IV. Stress from thermal nitridation and epitaxial growth were investi-

gated and modeled. After developing models for stress in the silicon substrate from a wide

variety of sources, it is useful to investigate the effect of this stress on bulk processing


Figure 5.1 illustrates a scaled MOSFET. The high dose implantation in the source

and drain leads to the formation of dislocation loops in those regions. As the devices get

scaled, stress effects from the nitride layers and isolation regions become important. The

loop evolution during the subsequent thermal anneal could be influenced by the stress

present in these areas. The loops effect device properties such as junction leakage current

and may cause yield related problems. The lateral diffusion of dopants under the channel

could also be affected by the presence of the stress and/or dislocation loops. Since the

dopant profile in the channel directly effects device properties such as threshold voltage

and sub-threshold slope, such an investigation would be useful for a technologist.