Processing, characterization and modelling of borosilicate glass matrix-particulate silicon nitride composites, containi...

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Title:
Processing, characterization and modelling of borosilicate glass matrix-particulate silicon nitride composites, containing controlled additions of porosity, for use in high speed electronic packaging
Physical Description:
2 v. : ill. ; 29 cm.
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English
Creator:
Randall, Michael S., 1963-
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Subjects / Keywords:
Materials Science and Engineering thesis Ph. D
Dissertations, Academic -- Materials Science and Engineering -- UF
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bibliography   ( marcgt )
non-fiction   ( marcgt )

Notes

Thesis:
Thesis (Ph. D.)--University of Florida, 1993.
Bibliography:
Includes bibliographical references (leaves 581-629).
Statement of Responsibility:
by Michael S. Randall.
General Note:
Typescript.
General Note:
Vita.

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University of Florida
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All applicable rights reserved by the source institution and holding location.
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aleph - 001938263
oclc - 30947317
notis - AKB4399
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Full Text












PROCESSING, CHARACTERIZATION AND MODELLING OF
BOROSILICATE GLASS MATRIX-PARTICULATE SILICON NITRIDE COMPOSITES,
CONTAINING CONTROLLED ADDITIONS OF POROSITY, FOR USE IN
HIGH SPEED ELECTRONIC PACKAGING




















By

MICHAEL S. RANDALL





















A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

1993


UNIVERSITY OF FLORIDA LIBRARIES



































Copyright 1993

by

Michael S. Randall















ACKNOWLEDGEMENTS


This work would not have been possible without the skilled help of

many individuals. First and foremost, I would like to thank my wife,

Sara, for her unconditional love, understanding and support. None of

this would have been possible without her. I would also like to thank

my parents (Randalls and Elders) for their support, understanding and

encouragement. I would like to thank my brothers and sisters for their

moral support as well.

On the technical side, I would like to sincerely thank Mr. Gary

Scheiffele for his vast amounts of training and advice in the area of

materials processing. I would like to thank R. Raghunathan and A.

Bagwell for their advice and creative discussions as well. Other

training and advice, in the area of materials processing, by Dr. M.

Amini, Dr. C. Khadilkar, Dr. T.S. Yeh, Dr. S. Vora, Dr. H.W. Lee, Dr. P.

Bendale, and Mr. M. Springate, are also greatly appreciated.

Furthermore, I would like to gratefully acknowledge the advice of Dr.

H.K. Ober, of Cornell University, in the area of dispersion

polymerization.

Complex impedance measurements were made possible through the

equipment and advice of Dr. L.L. Hench, Dr. J.K. West, and Dr. S.

Wallace, at the Advanced Materials Research Center (AMRC). Solution

(ICP) and surface (FTIR) analysis was also most graciously provided by

Dr. L. Hench and Mr. G. LaTorre. Technical advice and support in the

area of electron microscopy (SEM and TEM) from Mr. W. Acree, Mr. R.

Crockett, Dr. Y.J. Lin and Dr. S. Bates is also acknowledged gratefully.

In addition, I would like to thank Mr. A. Cozzi and Dr. D. Clark for

advice and support in doing thermal oxidation experiments. Processing

equipment and support was provided by Dr. M.D. Sacks.








I would like to sincerely thank my advisor, Dr. J.H. Simmons, for

all of his input and support. I would also like to acknowledge the co-

chairman of my committee, Dr. M.D. Sacks for his advice and support. I

would like to thank the rest of my committee, Dr. P.H. Holloway, Dr.

L.L. Hench, and Dr. D.E. Burke for their assistance as well.

Finally, I would like to thank the Engineering Offices of Gould,

Lewis and Proctor, as well as AVX Corporation for providing me

employment so that I could pursue my degree during difficult financial

times.
















TABLE OF CONTENTS
Page

ACKNOWLEDGEMENTS ......................................... .... iii

ABSTRACT ....................................................... x

CHAPTER ONE: INTRODUCTION ...................................... 1

1.1 The Impact of Electronics on Modern
Civilization ......................................... 1

1.1.1 Economic and Political Aspects ......... 1
1.1.2 The Future of the Electronics Industry:
Impact and Limitations ................. 2
1.1.2.1 The Fourth Generation ...... 2

1.2 Fundamental Microelectronic Packaging
Limitations ........ ....... .......................... 5

1.2.1 Electron Light Speed Limit ............. 9
1.2.2 Conductor Spacing Limit ................ 9
1.2.3 Cooling Limitations ................... 13

1.3 Electronic Packaging: Overview of the Field ....... 18

1.3.1 History ..... ........... ............ .. 18
1.3.2 Importance of the Electronic Package ... 24
1.3.2.1 Economic ................... 24
1.3.2.2 Functional ................. 24
1.3.3 Properties Desired of Packaging
Materials ...... ....................... 27

1.4 Materials Solutions to Electronic Packaging
Problems ........................................... 40

1.4.1 Ceramics versus Polymers .............. 40
1.4.2 Methods and Materials .................. 43
1.4.2.1 Traditional ................ 43
1.4.2.2 Advanced .................. 44

1.5 Proposed Packaging Material System:
Statement of Thesis ............................... 51

1.5.1 Choice of Electronic Packaging Material
System ................................... 51
1.5.2 Topics of Investigation ................ 53








Page

CHAPTER TWO: THEORETICAL AND TECHNICAL REVIEW ................ 75

2.1 Overview ...... ..... ............................. .. 75

2.2 Synthesis and Processing of Uniform Polystyrene
Latex Microspheres (UPLMs) ......................... 75

2.3 Particle Packing ................................... 85

2.3.1 Monosized Spheres ...................... 85
2.3.1.1 Ordered Packing ............ 85
2.3.1.2 Random Packing ............. 85
2.3.2 Packing of Multimodal, Discrete
Distributions of Spheres .............. 88
2.3.3 Continuous Size Distribution Particles 105
2.3.3.1 Ideal Packing .............. 105
2.3.3.2 Hindered Packing ........... 110
2.3.4 Effects of Settling and Segregation .... 110

2.4 Clustering and Percolation Theory .................. 112

2.4.1 Clustering ............................ 115
2.4.2 Percolation .................. ........ 116
2.4.3 Application of Percolation to
Microstructure ......................... 123

2.5 Sintering ............. .......... ................... 134

2.5.1 General ................................ 134
2.5.2 Viscous Sintering ...................... 140
2.5.2.1 Viscous Sintering of
Real Systems ............... 149
2.5.2.1.1 Effects of
Microstructure ....... 149
2.5.2.1.2 Viscous Sintering of
Glass Matrix
Composites Having
Nonsintering
Inclusions ........... 153

2.6 Dielectric Theory .................................. 158

2.6.1 Dielectric Materials ................... 158
2.6.2 Measurement of Dielectric Properties ... 163
2.6.3 Dielectric Properties of Composite
Materials ............ ................. 170

2.7 Mechanical Properties ............................. 179

CHAPTER THREE: EXPERIMENTAL PROCEDURE ........................ 184

3.1 Overview .......... .............................. .. 184

3.2 Powder Synthesis and Treatment .................... 184

3.2.1 Overview ..................... ........ 184
3.2.2 Synthesis, Characterization and
Preparation of Polystyrene Microspheres 184
3.2.3 Milling and Preparation of Borosilicate
Glass Powder .......................... 199








Pace

3.3 Powder Characterization ........................... 202

3.3.1 Overview ................................ 202
3.3.2 Visual ....... ......................... 203
3.3.3 Density .................................. 204
3.3.4 Size Characterization of Ceramic
Powders ....... ... ..................... 206
3.3.5 Surface Area .......................... 209
3.3.6 Chemical .............................. 220

3.4 Suspension, Casting and Green Compact Studies ...... 224

3.4.1 Overview ........ .. ... ....... ......... 224
3.4.2 Wet Processing and Characterization .... 225
3.4.2.1 Selection of the Dispersion
System ........ ....... .... 225
3.4.2.2 Characterization and
Optimization of the
Suspension System .......... 228
3.4.2.2.1 Overview ............. 228
3.4.2.2.2 Rheology of Dispersed
Composite Components 228
3.4.2.2.3 Optimization of the
Suspension System ... 230
3.4.2.2.4 Effects of Sonication
and Aging Upon
Suspension Properties 232
3.4.2.2.5 General Rheology
Studies .............. 235
3.4.3 Slip Casting of Compact Samples ........ 236
3.4.4 Suspension Solids Loading Determination 242
3.4.5 Characterization of Green Compacts ..... 243
3.4.5.1 Visual ..................... 243
3.4.5.2 Hg Porosimetry ............. 243

3.5 Thermal Analysis: Oxidation and Pyrolysis Studies 249

3.5.1 Overview ............. ................. 249
3.5.2 Oxidation Studies ...................... 250
3.5.3 Pyrolysis Studies ..................... 251

3.6 Thermal Treatments ................................. 252

3.6.1 Furnace Calibration ................. 252
3.6.2 Pyrolysis and Presintering ............. 258
3.6.3 Sintering .................. ............ 259

3.7 Materials Characterization ......................... 261

3.7.1 Archimedes Density Characterization .... 261
3.7.2 Dielectric Properties Characterization 267
3.7.3 Microscopic Investigation of Composites 277
3.7.3.1 Overview ................... 277
3.7.3.2 Specimen Preparation ....... 277
3.7.3.3 Investigation of Segregation
of Included Porosity ....... 281
3.7.4 Mechanical Properties Data ............. 281


vii








Page

CHAPTER FOUR: RESULTS AND DISCUSSION ......................... 286

4.1 Precursor Powders .................................. 286

4.1.1 Visual ....................... .......... 286
4.1.2 Powder Density ........................ 295
4.1.3 Particle Size/Size Distribution ........ 298
4.1.3.1 Polystyrene Microspheres ... 298
4.1.3.2 Ceramic Powders ............. 315
4.1.4 Powder Surface Area .................... 323
4.1.5 Effect of Ball Milling On BS Glass ..... 326

4.2 Suspension and Green/Pyrolyzed Structure
Characterization ....................................... 337

4.2.1 Suspension Characterization .............. 337
4.2.3 Green/Pyrolyzed Structure
Characterization ...................... 349
4.2.3.1 Overview ................... 349
4.2.3.2 Structural Characteristics
of Polystyrene Latex
Compacts .................. 349
4.2.3.3 Structural Characteristics
of Green and Pyrolyzed
Composites ............ ..... 360
4.2.3.4 Effects of Aging and
Sonication Upon Green
Properties ................. 382
4.2.3.4.1 Sonication ........... 382
4.2.3.4.2 Aging ................ 386

4.3 Thermal Processing and Characterization ............. 395

4.3.1 Removal of Organics ................... 395
4.3.2 Evolution of BS Glass Surface Area ..... 399
4.3.3 Oxidation of Si3N, Powder ................ 404
4.3.4 Sintering .............................. 408

4.4 Characterization and Modelling of Processed
Materials .......................................... 450

4.4.1 Characterization of Microstructure ..... 450
4.4.2 Modelling of Included Porosity .......... 482
4.4.3 Characterization of Dielectric
Properties .................. ... ....... 499
4.4.4 Microhardness Characterization ......... 534

CHAPTER FIVE: SUMMARY AND CONCLUSIONS ......................... 542

5.1 Overview ............. ....... .. .................... 542

5.2 Powder Development and Characterization ............ 542

5.3 Green Processing and Characterization .............. 543

5.4 Thermal Processing and Characterization ............ 544

5.5 Characterization and Modelling of Densified Compacts 546


viii











CHAPTER SIX:

APPENDIX I:


APPENDIX II:



APPENDIX III


APPENDIX IV:


SUGGESTIONS FOR FUTURE WORK ......................

MANUFACTURER'S DATA FOR CERAMIC CONSTITUENT
POWDERS ...........................................

PARTICLE SIZE AND SIZE DISTRIBUTION DATA
OF UNSETTLED 4.6 pm REGIME (061990 SERIES)
UPLM SPHERES ................................. ....

LEAST SQUARES POLYNOMIAL REGRESSION DATA
CURVE FITTING PROGRAM (BASIC) ...................

LIST OF ACRONYMS .................................


REFERENCES .....................................................

BIOGRAPHICAL SKETCH ............................................


Page

549


553



564


576

579

581

630















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

PROCESSING, CHARACTERIZATION AND MODELLING OF
BOROSILICATE GLASS MATRIX-PARTICULATE SILICON NITRIDE COMPOSITES,
CONTAINING CONTROLLED ADDITIONS OF POROSITY, FOR USE IN
HIGH SPEED ELECTRONIC PACKAGING


By

Michael S. Randall

August 1993

Chairman: Dr. Joseph H. Simmons
Major Department: Materials Science and Engineering


Borosilicate glass matrix-particulate silicon nitride composites,

with controlled additions of porosity, are produced through suspension

processing and slip casting of nonaqueous, codispersed suspensions.

Controlled porosity is obtained via the addition and pyrolysis of

polystyrene latex microspheres. The effects of latex size and size

distribution upon controlled pore structure are investigated. The

largest (9.0 ym monosized) latex, at a concentration of 17.6 V%, is

found to give the largest amount of closed porosity (15.6 V%).

The borosilicate glass-silicon nitride binary is also investigated

in order to determine the effect of nonsintering inclusion concentration

upon processing factors as well as upon final composite properties.

Composites containing all three constituents (borosilicate glass, Si3N4,

and polystyrene latex) are also investigated.

Above the percolation threshold of latex addition (i.e. a filled

fraction of approximately 16 V% of total space), the pore structure is

observed to change rapidly, greatly affecting densification behavior as

well as the pore structure. Additions of latex below the percolation








threshold result in hermetic, densified structures subsequent to

processing. Silicon nitride additions are found to retard densification

kinetics at and above concentrations of 16 volume percent of total space

and to arrest sintering at and above Si3N4 concentrations of 36 volume

percent of total space, in accordance with viscous sintering theory.

Hermetic, porous borosilicate glass-particulate silicon nitride

composites are produced having maximum closed porosities of

approximately 15.6 volume percent (at approximately 16.0 V% total

porosity). The densified included pore structure is accurately modelled

using a modification of standard series clustering and percolation

models.

Corresponding minimum composite dielectric constants of

approximately 3.5 are observed. The dielectric constant of the

composites are found to be stable over the range of frequencies

measured. Dielectric loss values are found to agree well with analogous

literature values for the borosilicate matrix glass. Composite

dielectric constants are modelled using effective medium theory as well

as traditional dielectric mixing rules.

Microhardness evaluations of representative composites are also

discussed. The elastic moduli of the composite system are modelled

using MacKenzie, linear regression, Voigt and Reuss models. Stoke's

settling theory is also extrapolated to explain the lack of segregation

observed in this system.















CHAPTER ONE
INTRODUCTION


1.1 The Impact of Electronics on Modern Civilization

1.1.1 Economic and Political Aspects

The electronics industry is a $460 billion industry world wide

[88SCH1]. The American electronics industry accounts for 38.1% of this

amount, while Japanese and European electronics industries account for

37.7% and 24.2% of the world electronics industry, respectively

[88SCH1]. Domestically, the electronics industry accounts for 3.6% of

the gross national product (GNP) which amounts to approximately 170

billion dollars [88SCH1, 90WRI]. The electronics industry is currently

growing at an annual rate of 13% for Japan, and 11% and 6% for the

United States and Europe, respectively [88SCH1].

Demand for improved electronic devices (i.e. higher speed, smaller

size, and greater ability, etc.) has provided a driving force for

continuous improvements in microelectronic technology. Never have Ralph

Waldo Emerson's words, "If a man can write a better book, preach a

better sermon, or make a better mouse-trap than his neighbor, though he

builds his house in the woods, the world will make a beaten path to his

door," been more applicable to an industry [88CAR, p. 84.8].

The electronics industry has generally progressed from analog to

digital electronics. The workhorse of digital electronics is the

integrated circuit. The IC was simultaneously invented by Jack Kilby of

Texas Instruments and by Robert Noyce of Fairchild Industries in 1958

[88MAC). The field of IC technology has grown through three generations

of successively increasing integration (i.e. MSI for medium scale

integration, LSI for large scale integration, and VLSI for very large

scale integration, respectively), with more generations to come (i.e.










ULSI and WSI, for ultra large scale integration and wafer scale

integration, respectively). Furthermore, IC devices are available in

many configurations, as required by the exhaustive number of electronic

appliance applications. The general trend in these electronic devices

is toward maximization of circuit elements per unit volume. Figure 1.1

illustrates the evolution of circuit density for both field effect (FET)

and bipolar junction (BJT) transistor IC devices. The relative scale of

integration is also indicated in Figure 1.1



1.1.2 The Future of the Electronics Industry: Impact and Limitations

1.1.2.1 The Fourth Generation

The major goals influencing the evolution of electronic technology

is to increase performance and universality of application. Digital

microprocessor-based devices dominate the electronics industry.

Therefore, improvements in electronic technology will focus upon

advancement of microprocessor technology as well as in advances in

microprocessor interlinking and increasing the availability and amount

of memory accessible by microprocessors. Other goals include reduction

in power consumption, reduction in device size and weight, increased

device capability as well as increased device dependability and

environmental/thermal stability. Other important requirements are the

maximization of device output and quality, at minimized cost.

The methods that will be used in order to achieve the above goals

will be quite varied [see 89SER,89TUM3, etc.]. In order to increase

computing speed (i.e. electronics performance), non-traditional

technologies, which are currently in their infancy, will be applied.

Examples of these technologies include optical switching and

communication (including holography) [89SER,88YAN,88SRI,87COR1,

87COR2,83BER], electro-optical interfacing [88HUT,87JIN], advanced

semiconductor materials, parallel processing [92SKE], artificial

intelligence (AI), integrated services digital networking (ISDN)












a

oC


O
L_,


6- T
VLSI
5








1 1 Hybrids

-1
0 Transjstors
Tu bes

1965 1970 1975 1980 1985 1990 1995
Year








re 1.1 Illustration of the increase in electronic circuit
density with time [91TUM]


Figu










[900HS], biological systems [89SER], neural networking [89SER],

superconductor-based logic and communications [89SER,89TUM3], etc.

Furthermore, electronic performance will be advanced via the

continued evolution of traditional technologies, in pursuit of

theoretical limitations. One goal is to reduce current packaging

hierarchies by at least one level, in order to reduce signal flight

distances. This change would result in a reduction in the number of

interconnects as well, thereby improving reliability and device

longevity, while reducing production costs. The first goal may be

achieved by successful implementation of another goal, which is to

economically obtain ultra large scale and/or wafer scale integration

(ULSI and WSI, respectively). Wafer scale integration results in a

dramatic increase in the scaling of microcircuitry, which, in theory,

leads to reduced signal flight times due to reduced signal transmission

distances. Ironically, however, WSI offsets some of the advantages of

removing a packaging level since production costs would definitely

increase. Furthermore, it would no longer be possible to replace one

individual chip since the smallest field replaceable unit (FRU) would

become the integrated wafer itself. As discussed below, there are other

drawbacks to WSI as well.

Another goal is to change to higher performance semiconductor

materials, having higher electron-hole mobilities, such as GaAs. It is

also preferred that the replacement semiconductor materials) be direct

band gap materials, thereby allowing more efficient usage of power as

well as less phonon-initiated heat generation.

Finally, a great deal of research effort is currently involved

with improving traditional microprocessor and packaging technologies.

The focus of such research is to increase the performance of

microelectronic systems beyond the state of the art and closer to

fundamental theoretic limitations, as discussed in section 1.2 below.

Increased clock frequencies; finer scales of microcircuitry; larger










scales of integration; larger, cheaper, and faster memories and

microprocessors; use of lower resistivity conductors as well as low

dielectric constant, cofirable packaging materials and implementation of

increased performance cooling designs and materials are all desired

goals of said research. Figure 1.2 illustrates the current and

projected trends in the performance of computers based upon traditional

silicon IC technology.

Furthermore, environmental concerns are becoming increasingly

important. Hazardous materials, involved in the production of

electronic appliances, must be properly disposed of or recycled. Also,

many of the cleaners and solvents used in IC production and electronic

packaging are being replaced by environmentally benign materials and

processes [89SER].

In summary, it is quite apparent that the microelectronics

industry has a great many opportunities for advancement. However, it is

also true that said industry is subject to unparalleled competition as

well as a great deal of regulation.



1.2 Fundamental Microelectronic Packaging Limitations

The fundamental limitations discussed in this section relate to

microelectronic packaging only. Surprisingly, the switching speed of a

microelectronic apparatus is as much a function of the packaging

configuration and materials as it is a function of the actual switching

devices. Figures 1.3 and 1.4 illustrate the theoretical limitations

that are involved in digital electronics, in a graphical sense, and are

a valuable summary as well as an illustration of the combination of each

fundamental limitation. The figures outline the perimeters that provide

the limits of maximum performance of a digital electronic system

(including switching devices, packaging, interconnection, etc.).









3




2 -- 5




.1 -- / 25 5
O -3








-1 2500




-2 I 'I II


Year










Figure 1.2 Current and projected trends in traditional, silicon-
based, computer performance [91TUM]
a-






-2














based, computer performance [9lTUM]

































-9 -7 -5 -3 -1 1 3


log {element spacing (m)}


Figure 1.3


Element spacing versus delay time plane of electronic
packaging space, illustrating the theoretical
limitations in electronic packaging performance with
respect to spacing of electronic lines and signal
elements [89SER]


-6



-8



-10


-12



-14
































-8 -6 -4 -2 0 2 4


log {element spacing (m)}


Figure 1.4


Depiction of the theoretical limitations encountered
in electronic packaging as defined by the electronic-
element-spacing versus signal-line-spacing plane of
electronic packaging space [89SER]


2


0


-2
C


S-


-6


-8


-101
-10










1.2.1 Electron Light Speed Limit

Electrons can not travel at speeds exceeding the fundamental speed

of light in a perfect vacuum (i.e. approximately 3 x 108 m/s or 186,000

miles/s), regardless of the medium that they travel through. Electrons

travel through perfect (lossless) conductors at the speed of light if

said conductor is surrounded by free space. However, if the perfect

conductor is surrounded by a dielectric medium other than free space,

the speed at which electronic signals will traverse the conductor is

expressed through the relation:








where K is the dielectric constant of the insulating material

surrounding said perfect conductor. From the above discussion, it is

evident that use of lossless, low dielectric constant insulating

materials, in combination with non-magnetic, nearly perfect conductors,

will increase electronic signal speed, and thus, overall performance.

Furthermore, it is important to minimize packaging scale (i.e.

miniaturization) in order to minimize the signal time of flight (TOF) at

the signal speed indicated by the above equation. Therefore, it is

important to carefully chose both the electronic packing material and

the packaging metallization, as well as to minimize the scale of

electronic packaging integration.



1.2.2 Conductor Spacing Limit

While the quantum electron tunneling limit is not currently in

danger of being approached, using traditional electronic packaging,

there are other limitations that do effect conductor spacing in

electronic packages. In any electronic package, there is a finite

amount of space available for signal transmission lines. It has been

shown [89SER,89TUM3,90SHI2,90SHII,91TUM] that as the number of switching










devices increases, the number of input-output signal lines (I/Os) must

also increase according to the relation:


I=bCP




where I is the number of I/Os, b is the average number of signal

connections per circuit, and p is a positive exponential (research has

found that p is always < 0.67 and is usually about 0.5). This relation

is commonly know as Rent's rule. In two-dimensional space (i.e. single

layer or double sided electronic packaging), this limit has already been

approached or exceeded using traditional thick film packaging

technology, and, in some cases, using thin film technology [89SER].

The conductor spacing limitation may be circumvented, to a certain

extent, by using three dimensional packaging. Multilayer packages,

having signal planes interconnected with vias, are an example of three

dimensional packaging. However, there are limitations even to

multilayer packaging systems. These limitations depend upon the size of

the interlayer vias used and the number of layers used [89SER].

The minimum size of signal traces is theoretically limited by

quantum effects. Realistically though, the actual size and separation

distance of signal traces is most often determined by the ability to

produce straight and smooth traces having a uniform cross section.

At high frequencies the skin effect limits electronic current to

the outside (skin) of a conductor. At said frequencies the skin depth

is on the order of the conductor diameter, thereby decreasing the

effective diameter of the conductor. This serves to increase resistive

losses. Furthermore, since the current traverses the outside (skin) of

the conductor, interruptions in surface smoothness have a much greater

effect upon signal integrity. At said frequencies, as the signal

changes from one medium to another, any change in conductor cross

section will further enhance attenuation and signal reflection.










Thus, it is important not only to match impedances, but also to match

signal cross section sizes and geometries in the frequency regime

characterized by significant skin effect. Other factors include,

switching energy (i.e. maximum current density) and switching frequency

as well as dielectric strength and hermeticity of separating insulators.

The homogeneity of the conductor material as well as the overall

conductor quality (i.e. its resistivity, magnetic susceptibility, and

characteristic skin depth as a function of frequency, etc.) is also an

important considerations when pursuing minimum conductor spacings.

Conductor spacing limitations are also affected by electronic

noise. There are four types of internal electronic noise possible in a

packaging system: inductive, capacitive, reflected and power

distribution or AI noise.

Reflected noise is a result of a mismatch in impedance between

signal traces and active devices. It is not significant until higher

frequencies are reached (i.e. above 10MHz). Reflections may be

eliminated by matching the impedance of all elements in the device. In

practice, however, this is quite difficult and design goals are toward

realistic minimization of reflections.

Power distribution (PDN) or AI noise results from the switching

process itself. As a device switches, it requires a certain amount of

power, (typically about 1--10 mW [91TUM]). In a microprocessor, it is

possible for many elements to switch simultaneously. Said switching

processes are fast, usually occurring in tens of nanoseconds.

Therefore, the current demand upon the power supply can be excessive and

may cause a drop in the supply voltage. This drop causes a voltage

pulse to be sent to the switching devices, due to the parasitic

inductance of each microcircuit. The voltage pulses, if significant,

cause spurious switching.

Power distribution noise may be reduced through use of high power,

self-regulating power supplies, reduction in parasitic inductances










through package design, increased power and ground availability,

reducing signal path lengths and placement of signal traces more closely

to power and ground traces, etc.

Perhaps the best way to reduce or eliminate AI noise is to place a

small capacitor, having very little parasitic inductance (i.e. a

decoupling capacitor), as closely as is feasible to the switching

elements themselves. Decoupling capacitors serve as a local current

source during periods of transience, reducing AI noise to acceptable

levels.

Both inductive noise and capacitive noise are types of coupling

noise. Both are resultant from current changes in adjacent signal

traces and may result in the phenomenon commonly known as crosstalk.

Inductive noise involves a single voltage pulse, travelling in the

opposite direction of the original signal, in signal traces neighboring

the element carrying the original pulse. Capacitive coupling noise

results in two pulses, travelling in opposite directions from each

other, in signal traces neighboring an active trace. The first pulse

travels in the direction of the parent pulse and the second in the

opposite direction. Both pulses are in phase with the parent. In the

reverse direction, capacitive and inductive elements interact. The

magnitudes of said pulses depend directly on the distance between the

conductive traces and in the dielectric permittivity of the material

separating the traces. The ability of these pulses to result in

crosstalk depends upon both the voltage and the width of the resultant

coupled noise pulses. Both types of pulses can cause erratic switching

if the pulse voltage exceeds either the forward or the reverse bias

(depending upon the pulse direction), of the switching elements in

question, for a duration long enough to switch the elements.

Furthermore, reflected coupled pulses may also interact with first order

coupled pulses. The entire process is quite complex to model and is

handled in several publications [89SER,89TUM3, etc.]. It is sufficient









here to note that reductions in dielectric permittivity of the

insulating material will reduce coupled noise in an electronic packaging

system. Furthermore, coupled noise may be reduced through utilization

of prudent design configurations and criteria [89SER].



1.2.3 Cooling Limitations

The issue of electronic device cooling is very involved. As chip

integration evolves, switching elements are placed with increasing

density. While per device power dissipation has steadily decreased, the

rate of decrease of microdevice separation has surpassed this effect

(see Figures 1.5, 1.6 and 1.7). As a result advanced ICs have cooling

demands that require cooling technology at or beyond the state of the

art. Figure 1.7 illustrates the increased trend in cooling requirements

for IBM microelectronic packages. The cooling limitation may well be

the theoretical limitation that is first reached.

One method to meet cooling needs is to use direct band gap

materials or superconducting Josephson logic configurations as switching

devices, since they do not dissipate as much switching energy in the

form of heat as do indirect bandgap solid state switching materials (see

Fig 1.8). However, these switching devices have many drawbacks which

limit their successful implementation.

Another method is to use high thermal conductivity packaging

materials. Both of the above methods are passive in nature and are

somewhat limited, however, because all switching materials dissipate

some energy as heat, and because efficient heat sinking as well as heat

transfer at interfaces are required, in conjunction with high thermal

conductivity materials. These requirements are due to the relatively

small difference between heat source and sink temperatures typical in

electronic packaging applications.

The most successful cooling methods utilized to date involve

active cooling, such as immersion technology [89SER]. A new method, not




















1000



0 15 1 1 1 100











Year
10 N







1970 1975 1980 1985 1990 1995

Year


Figure 1.5


Increase in chip signal connections (i.e. device
integration) and chip size with respect to time
[91TUM]


10000


1000



100


10


0
C
.2-0
.C
U
So>
0 0
Oc
L0

-ro


C)


1 L
1965
























































Figure 1.6


10 100 1000 10000


Heat Dissipation (W/cm2)
















Illustration of IC power density as a function of chip
integration [91TUM]






































1965 1970 1975 1980


1985 1990 1995


Year


Figure 1.7


Cooling ability (i.e. requirements) of IBM electronic
packages as they have evolved with time (i.e.
increased packaging integration) [91TUM]


C4'



C
Cu


0

a.
o
a,


0)
Q.,

()

,.


0L
196


Model 900 (390/9000)









Model 3090S (TCM)

Model
Model Model 3081 Model
Model 370 3033 (TCM) 3090
360 (TCM)
I I I I


.0















-8


0


E

u,

O
a,


-9


-10


-11


-12


Figure 1.8


-7 -6 -5 -4 -3 -2 -1

Power Per Gate (log{W})











Comparison of different switching device technologies
with respect to device power dissipation [91TUM]


Key:
Si-Silicon
GaAs-Gallium Arsenide
HEMT-High Electron Mobility Transistor










currently used in production, but showing great promise, is that of

microchannel cooling [89SER]. Microchannel cooling involves routing

coolant through the back of the IC chip itself. The chip is modified by

etching microchannels into its back, using traditional lithography

techniques. A plate is then affixed to the chip back, enclosing the

channels. Manifolds are then affixed to the chip ends, allowing flow of

coolant through the microchannels. This technique allows for a heat

dissipation of approximately 600 W/cm2 using water, flowing at the rate

of 10 cm3/s, and using a temperature differential of 600C and has

exhibited a heat exchange as high as 870 W/cm2 [89SER]. Using the

treatment outlined in [89SER], this cooling technology could allow for a

minimum nearest-to-next-nearest propagation delay time of 5 x 10-13 s

without overheating, using the logic restoration basis theoretical

minimum switching energy (E,,) of 7.7 x 1015 J. This could allow for a

theoretical maximum switching frequencies in the THz range (if only a

few switching elements are involved).



1.3 Electronic Packaging: Overview of the Field

1.3.1 History

Electronic packaging was first used, in significant amounts, in

Hollerith's card reader [89SER]. The mechanical relays utilized in the

machine had slate mounting plates as well as varnish covered solenoid

wires. Electronic packaging has advanced a great deal since then. Many

packaging changes have been implemented between Hollerith's

electromechanical relay-based technology and today's solid state

electronics. This section covers packaging methods used only since the

introduction of solid state logic.

Until very recently, emphasis for advancement in the field of

electronic packaging was limited to the scale of integration of solid

state devices. Contemporary chips incorporate up to several million










logic or storage elements, and thus, have eliminated the need for

several hierarchies of packaging that were formerly necessary.

Standard modular system (SMS) technology was the first concept

introduced for solid state device packaging [89SER]. This technology

interconnected singular electronic devices (i.e. transistors,

capacitors, etc.) on a printed circuit board. It was developed in 1959

and afforded a far superior alternative to tube technology in speed,

size, power consumption and reliability. The circuit boards were

connected to a panel and interconnected via wrapped wire and cable

connections. Apparatii utilizing this technology were still quite

limited, however, and a great deal of effort has since been expended

attempting further integration. With the invention of the IC a new

implement was provided for use toward this goal.

Solid logic technology (SLT) introduced many of the technological

advancements that are used, in modified form, today in ceramic packages.

The package was made from 96% A1203, 4% glass, and used swaged pin

technology. The chip was soldered in place, then encapsulated using a

metal cap held in place with epoxy. The method of chip attachment

utilized was called the controlled collapse chip technology (C4) which

involves depositing solder balls on either the IC or the package I/O

pads, flipping the chip face down upon the ceramic package carrier, then

heating the assembly to let the solder flow and attach the chip to the

package. This process is also known as flip-chip technology and is used

frequently today [89SER,88TUM,89TUM,91TUM].

Advanced solid logic technology (ASLT) improved upon SLT by

screening conductors onto both sides of the substrate. Furthermore, the

substrates were made stackable by soldering the pins from the bottom of

one package to the top of another. The wiring density was also

increased. All these advances yielded significant performance increases

[89SER,88TUM,89TUM). Monolithic systems technology (MST) further








20

expanded upon this technology. This system basically replicated SLT and

ASLT but provided further integration. The MST package provided 18

I/Os.

Vendor transistor logic (VTL) technology helped to introduce the

first universal industry standard for ICs [88TUM]. A variation upon

vendor transistor logic, card on board (COB) technology, allowed

manufacturers the ability to produce electronic appliances using

prepurchased ICs. Thus the precedent was established for second party

electronics, opening a huge industry and bringing the concept of

component interchangability to integrated logic-based components.

Initially ICs were available with up to fourteen leads. Later,

planar or dual in-line packages (DIPs) were developed having as many as

64 leads (88TUM,89TUM]. The DIPs were plugged into cards, which also

included other active and passive elements. The cards were plugged into

boards and the boards connected to a gate. The gates provided power as

well as interconnection [89SER].

Metallized ceramic (MC) technology was the first packaging genre

to utilize photolithographic techniques. As circuit integration

increased, I/O density requirements mandated that either thin film or

multilayer technology be utilized [88TUM,89TUM]. Metallized ceramic

technology used the former. The thin films were deposited by either

sputtering or thermal evaporation on both sides of an A1203 substrate.

The deposition process involved a three-layer deposition of chromium on

copper on chromium. The chromium layers were thin and were used to

improve adhesion on the inner layer [88TUM,89TUM].

Metallized ceramic polyimide (MCP) technology was the first

multilayer thin film technology. A polyimide layer was added to the top

of a ceramic substrate, and the polymer surface was deposited with

chromium then copper then chromium as above. This process was repeated

for several layers, then standard photolithographic techniques were










utilized to etch via spaces between layers. The vias were then back

filled with paste, thereby connecting the layers [89SER].

The discussion until now has been centered around the first level

of packaging hierarchy. Evolution of chip packages (the zeroeth level),

specifically LSI packaging, will now be discussed briefly in order to

introduce the next generation of first level packaging. Early large

scale integration (ELSI) involved packaging of 100 to 500 circuits, and

utilized pluggable module packaging, making it a field replaceable unit

(FRU) [89SER]. Large scale integration (LSI) technology was introduced

in 1979. The first LSI circuits contained 704 switching elements. The

chips had a switching speed as fast as 1 ns. Because the packages had

delicate I/O terminations, they were mounted to the first level module

utilizing wave soldered through holes. Up to nine LSI chip packages

were mounted to a single multilayer ceramic (MLC) module in this manner.

The MLC had been developed in order to accommodate ever increasing

chip integration levels. With up to 23 layers, the MLC presented a

technologically challenging processing hurdle. Multilayer ceramic

packaging technology was borrowed from the field of multilayer

capacitors, originated by RCA in the late 1950s [88TUM,89TUM]. Also

borrowed from the multilayer capacitor community was the concept of the

interlayer connection, or via, as well as tape casting and laminating

technologies [88TUM,89TUM]. Variations of MLC technology are still

utilized today. The basic process of MLC fabrication is outlined in

Figure 1.9 for both the old and new thermal conduction module (TCM)

production process. Said technology has been very successful in the

area of advanced performance ceramic packaging and is expected to

dominate that field, in varied form and in conjunction with thin film

multilayer polymer technology, in the future. There are excellent

literature sources which describe the process and related fields in

detail [82BLO,84BLO,84SCH2,88TUM,89SER,89TUM,91TUM].



















Raw Materials

Slurry Preparation
i
Casting and Blanking

Via Hole Punching

Metallization (Thick Film)

Stacking/Registering

Lamination

Organics Removal
and
Sintering
i
Final Ceramic
i
Electrical Tests

Attachment of Pins
and Flange

Substrate Machining
and Surface Treatment

Chip Attachment (C-4 Process)

Electrical Testing of Module

Final Module Assembly

Helium Gas Filling of Module


Alumina/Mo Based TCM Glass-Ceramic/Cu Based TCM


Alumina + Glass (4-10%)


Glass Powder


Acid-Base Acid-Acid

Continuous Casting Continuous Casting

Mechanical Mechanical

Mo Paste Cu Paste

Automated Automated

Automated Automated


Controlled Steam Atm.
Controlled Hydrogen Atm.
Crystallization Step

Alumina + Glass Glass Ceramic

Automated Automated

Automated
Automated
Ni and/or Au Plating

Seal Flange Top and Bottom Surface
Finishing and Seal Flange

Automated Automated

Automated Automated

Automated Automated


Automated


Automated


Figure 1.9


Flow chart of the MLC production process used in the
IBM TCM [82BLO,89TUM,91TUM]










Perhaps the best known example of MLC technology is the IBM TCM

series. When introduced in 1981 for the IBM 3081 computer system, the

IBM TCM used 96% alumina (4% glass) as the dielectric and either Mo or W

metallurgy [89SER,83BLO]. The multilayer module consisted of 33 layers

and could accommodate up to 118 IC chips. The layers were configured as

either signal (X or Y plane), redistribution, or voltage-reference

layers. Said module had up to 320 cm of wiring per cm3 of package.

Furthermore, an ingenious cooling device was utilized on the IBM TCM

which used chilled water forced through a hermetically sealed and He

backfilled chamber. Said technology was capable of accommodating chip

heat dissipations as high as 3 W/cm2. Much of the cooling ideologies

used in the original TCM (for the 3081) are used in the current TCM.

The state of the art TCM (introduced in 1991 for the IBM 390/9000)

seems only subtly different from the original TCM. However, it exhibits

markedly improved performance, by utilizing Cu metallurgy as well as low

sintering temperature (-1000C), low K (-5) crystallizable dielectric

materials cordieritee with minor clino-enstatite). Furthermore, the

390/9000 TCM can accommodate up to 121 LSI chips, and has 63 wiring

layers as well as 9 polyimide signal redistribution layers. All of this

was accomplished using special processing to avoid oxidation of the Cu

metallurgy during thermal treatment. The CTE of the dielectric used in

said package was matched carefully to Si over a broad range of

temperatures [91KUM2]. The packaging heat accommodation was increased

to -18 W/cm2 as well. This TCM represents the current state of the art

in high performance electronic packaging, although other corporations

have also marketed excellent examples [88BAB,89EMU,89SAW,89SER,89TUM3,

91SHE2,etc.].










1.3.2 Importance of the Electronic Package

1.3.2.1 Economic

Electronic packaging and interconnects account for a large portion

of the advanced ceramics market. The electronic ceramics market is the

largest niche within the field of advanced ceramics [91SHE2]. The

electronic packaging and interconnects market accounts for approximately

0.05% of the GNP of the United States [90WRI]. This industry involves

over $2.7 billion annually, accounting for approximately 1.5% of the

total sales of the entire US electronics industry [88SCH1,91SHE2].

Furthermore, the electronic packaging and interconnects industry

currently is experiencing a growth rate of approximately 8.5% per annum

[91SHE2], projecting a total market value of approximately $6.5 billion

by the year 2000 [91SHE2].



1.3.2.2 Functional

Upon first inspection, electronic packaging seems deceivingly

simple. The components of the package are passive and the final

packaged structure usually seems like an elementary monolith. Upon

further inspection, however, one learns that the electronic package is

quite complex. Perhaps no other type of passive device is subject to as

many material and environmental constraints.

Electronic packaging is typically divided into as many as six

levels. The zeroeth level of packaging involves the IC chip itself

(i.e. intra-chip integration), while first level packaging involves the

I/Os of the IC chip (i.e. chip level integration). In many instances,

the zeroeth order is not considered packaging, since it is inherent in

the chip integration itself. First level packaging brings power and

signal lines to the IC chip while providing mechanical and hermetic

protection.

The second level of the electronic packaging hierarchy involves

the interconnection between IC chips as well as other on-card devices











(i.e. card level integration). Second level electronic packaging is

task oriented, in that it involves the interconnection of electronic

devices that perform a specific task (i.e. video cards, etc.). The

second level allows for task diversity (i.e. different cards for

different tasks) as well as traditionally offering the smallest scale of

easy replacability (i.e. the field replaceable unit (FRU)). The third

level of packaging involves interconnection of cards (i.e. board level

integration) and the fourth level in the electronic packaging hierarchy

involves the interconnection of boards (i.e. gate level integration).

Finally, gates are interconnected to form a main frame in the fifth

level of the packaging hierarchy.

As digital systems have evolved, some of these packaging levels

have been eliminated. For instance, personal computers (usually denoted

card on board (COB) systems) do not have a fourth level of packaging.

Use of multichip modules (i.e. chip on board (also COB) systems) also

eliminates the second level in the electronic packaging hierarchy.

Eventually, the board level may be partially replaced as well if wafer

scale integration (WSI) comes to fore.

An electronic package basically provides a fixed structure for

active electronic devices. Said structure is subject to many, varied

constraints. The structure must be mechanically strong in order to

protect the delicate active devices from shock and external forces. The

package must also provide shelter from moisture and corrosive

environments. Furthermore, the thermal expansion of the electronic

packaging material must be similar to that of the active materials that

it packages, so that the packaging does not destroy its active occupants

when changes in overall temperature, or temperature gradients are

experienced.

The electronic package must also provide for one or more means of

dissipating heat generated by the active components. Heat dissipation

may be either passive or active. For either type of cooling, it is best










(although not mandatory) that the electronic packaging have a high

thermal conductivity. A high thermal conductivity is beneficial when it

is desirable to avoid thermal shock of the device. Furthermore, by

utilizing packaging materials having high thermal conductivities, heat

generated via the active devices is spread more quickly and more

homogeneously throughout the package, thereby avoiding detrimental hot

spots.

The packaging must also provide a satisfactory medium for

encapsulating power and signal transmission elements. As a result of

the current emphasis upon device miniaturization, this packaging

requirement has become quite important. Electrically conductive

elements have decreased greatly in height, width and pitch now that high

conductivity metals are being utilized, resulting in the need for

packaging materials having exceptional surface smoothness, interlayer

planarity [90REC] and either minimal or predictable shrinkage and

warpage during processing. In ceramic materials, these goals may be

attained only with proper processing. It is desirable that the starting

ceramic powders be very small in size and that said powders consolidate

to a very high green density. Furthermore, the consolidation must not

result in particle segregation.

The electronic package must also provide a medium that is suitable

for high quality electronic communication, since the electronic devices

housed in the package require "clean," constant power and high quality

signals. With the current emphasis upon increasing signal speed, this

requirement has mandated changes in both materials and design in order

to obtain satisfactory packages. As discussed below, this criterion

presents perhaps the greatest impediment to advancement in the field of

high speed computing.










1.3.3 Properties Desired of Packaging Materials

Table 1.1 summarizes both the requirements and the weight of said

requirements for electronic packages and packaging materials.

Surprisingly, the major barrier to the realization of the next

generation of high performance computing lies in limitations in

packaging materials and not in switching materials [83VEN,87MOH,87SHI,

87YAR]. The unavailability of satisfactory high speed electronic

packaging materials results from the fact that successful candidates

must satisfy several stringent criteria. First and foremost the

candidate must have satisfactory dielectric property requirements. The

dielectric constant and loss tangent must be low (3 to 5 or below, and

<0.005, respectively [86CRO,87KEL,87MOH,88GER3,89LEA]), and stable at

the frequencies used (MHz to tens of GHz [87YAR]). There are several

reasons for the dielectric properties criterion. The time delay (Td) of

signal propagation of an electronic pulse through a circuit element is

given by the relation:



Td c




where K is the material dielectric constant, L is the propagation

distance, and c is the speed of light [84SCH3,84SCH4]. Thus the signal

delay is proportional to the square root of the dielectric constant of

the surrounding packaging material. This effect is illustrated for

various ceramic materials in Figure 1.10.

The characteristic impedance (Z,) of package signal traces must

rest within a narrowly defined field of approximately 40 to 110 0

[89TUM3] (the most preferable value is 50 0 [88BAL]) due to noise,

signal delay and current draw considerations.










Table 1.1

Requirements and Importance of Said Requirements
for Electronic Packages and Packaging Materials [91TUM]


High Performance Applications

Property Importance Importance
Weighting

Dielectric Constant (minimize) Highest 5

Wiring Density (maximize) Highest 5

Metallization Conductivity Highest 5
(minimize)

Coefficient of Thermal Expansion High 4
(match to IC chip material)

Dimensional Control (maximize) High 4

Mechanical Strength (maximize) Medium-Low 2

Low Performance Applications

Property Importance Importance
Weighting

Cost (minimize) Highest 5

Thermal Conductivity (maximize) Highest 5

Coefficient of Thermal Expansion High 4
(match to IC chip material)

Wiring Density (maximize) Medium 3

Mechanical Strength (maximize) Medium-Low 2



















-. U


Key:


Ceramics in Production
Experimental Ceramics


+ Glass-Ceramics


Mullite


Alumina
Aluminum Nitride



te



Alumina + Glass Systems


-' IBM Cordierite/Clinoenstatite


J Cordierite + Glass
- Silica + Borosilicate Glass
Porous Silica


4 R 7 R 9 10


Dielectric Constant


Figure 1.10


Depiction of propagation delay time versus dielectric
constant for various ceramic materials [91TUM]


Mullil








30

Figure 1.11 graphically illustrates the design criteria for selection of

package characteristic impedance.

Furthermore, the minimal thickness of packaging layers between

circuit elements required for impedance matching is lowered when a lower

dielectric constant material is used, due to the following relation:



zo-





where Z0 is the characteristic impedance, L is the inductance associated

with the signal line, and C is the capacitance associated with the

signal line [84SCH3,84SCH4]. By lowering K, C is reduced per unit

thickness, thereby increasing Zo per unit thickness. Thus a thinner

packaging layer may be utilized while maintaining the characteristic

impedance, further enhancing miniaturization. Therefore, use of low K

packaging materials allows for increased digital performance in two

ways, by increasing signal speed and by helping to decrease signal

propagation distance.

The dielectric loss factor must also be low, as illustrated by the

relation:


P=C E'f Vj tan (6)




where P is the power loss due to dielectric loss, f is the signal

frequency, e' is the real portion of the material dielectric

permittivity, V. is the peak signal voltage and 6 is the dielectric loss

angle (e''/E') [76KIN]. From the above relation, it is evident that

power dissipation due to dielectric loss may become rampant at high

frequencies if insulating materials are not chosen carefully.

Utilization of materials having low K and tan(6) values also aids

(along with correct design of ground planes) in lessening problems of





















0.6

0
0.4 -
o


0.2 -
.0
o
Z
0.0
0























Figure 1.11


0.6

Noise Tolerance (volts)
Acceptable Design Area
Total Noise (volts) 0.4 CD
r .. n 0.4



0.2
S I --Total Delay Adder (ns)
S.'---hmpedance Limits
II I' 0.0
20 40 50 60 80 100 120

Board Characteristic Impedance (ohms)





















Depiction of design considerations for choosing a
package characteristic impedance [89TUM3]










crosstalk, signal pulse rounding and other phenomena leading to signal

infidelity [87MOH,87YAR,89SER,89TUM,89TUM3,91TUM].

A second goal in the design of electronic packaging is one of

expense reduction. In order to reduce production expenses, packaging

materials should be developed that are processable at low temperatures.

Lower processing temperatures also allow for use of nonrefractory metals

(such as silver and copper) as conductive elements. This is

advantageous from a performance point of view, since silver and copper

have relatively high electrical conductivities (6.31 x 107 and 5.96 x 107

(Ohm--m)" respectively [85CRC]). Therefore, both resistive heating and

signal loss would be reduced through the implementation of either

conductor material. Thus, cofirability with copper or silver is

advantageous from both cost and performance standpoints. Cofirable

systems must be totally processable at temperatures significantly below

the melting point of the metallic constituents (1083C and 9820C for

copper and silver respectively [85CRC]). Furthermore, cofirable

packaging materials must allow for processing treatments which ensure

the total pyrolysis of organic, as well as the complete sintering of

the metallization, while not adversely affecting the desired properties

of the conductor metallurgy.

The coefficient of thermal expansion (CTE) also should be matched

closely to that of the semiconductor material utilized. This ensures

that the chip bonds will not fail with repeated usage (i.e. when the

power is turned on and off). The induced plastic strain (ep)

experienced by the solder connections during thermal cycling of a chip

and package assembly is quantified by the relation:


A CTEx A TxD
p H


where ACTE is the difference in the coefficient of thermal expansion










between the IC chip and the packaging material, AT is the difference

between the temperature at which there is no stress and the temperature

of interest, D, is the distance from the neutral point of shear stress

on the chip (i.e. the horizontal middle), and H is the height of the

solder pad [84SCH2]. From this relation the number of cycles to failure

(Nf) may be estimated from the Coffin-Manson equation:

1

Ep




where A and m are constants whose values must be empirically determined

for the particular system [89TUM3].

From the above relations, it is evident that reducing the

difference in CTE between the chip and the package will reduce thermal

fatigue. Figure 1.12 illustrates this equation for several materials.

Also, plastic shear strain on the solder connections increases toward

the outside of the IC chip (i.e. as D, increases). Therefore thermal

cycling fatigue increases in magnitude with the use of larger IC chips

(i.e. VLSI). Not as obvious in this discussion is the effect of thermal

conductivity of the materials involved. Low thermal conductivities tend

to increase stresses within the packaging material but tend to decrease

ep by decreasing AT at the chip-solder-package interface. For this and

many other reasons, it is considered most prudent to use cooling methods

which extract heat from the back of the chip rather than through the

substrate.

Thus it is desirable to have a CTE which is adjustable for

different switching materials. Since Si is, by far, the predominant

switching material currently in use, the most utilitarian electronic

packaging materials will have a CTE that is customized to match that of

Si. Furthermore, it is important to match the CTE of Si over all

temperatures that the chip-package assembly will experience.













100000




10000




1000




100




10


- C
w,


Mullite + Silica + Alumina
Aluminum Nitride
Alumina + Borosilicate

Alumina

Epoxy-Kevlar



Polyimide-Glass

Epoxy-Glass



Coffin--Manson Equation


h.b


0 4.0


8.0 12.0 16.0 20.0 24.0


CTE (ppm/ 0C)


Figure 1.12


Illustration of the Coffin-Manson equation for several
materials [91TUM]


a)
U-



--

(D
3_
0)

LL.













Figure 1.13 exhibits the CTE of Si with respect to temperature.

Adjustability of CTE may be provided to varying extent by using ceramic

composite systems as packaging materials.

Furthermore, stress resultant from CTE mismatch is reduced between

packaging and metallization when lower firing temperatures are used (as

in low temperature, cofirable systems) by reducing AT. Differential

stress between metallization and packaging may be further reduced if

packaging materials that densify via a viscous sintering mechanism are

used, since localized stress may be alleviated if an annealing step is

used at temperatures slightly above the glass transition (T,) of the

packaging material. Stress on chip pads may be relieved similarly if

the chip bonding material requires heat treatment above T, of the matrix

glass.

The fourth desirable property of an electronic packaging material

system is that of high surface smoothness. Surface roughness may cause

disabling discontinuities within the package. Acceptable surface flaws

are usually no larger than about one tenth the metallization width

(typically >50 pm, [89SER,89TUM3]). As technological advances allow for

further miniaturization (i.e. substitution of photolithography for

screen printing as the application method for circuit metallizations

[90NEB]) this limit will surely decrease markedly.

Hermeticity is also desirable in a satisfactory packaging system.

If atmospheric moisture enters the package, dielectric properties will

change markedly [89SER,89TUM3,91WAL]. Moisture also contributes to

corrosion (and thus embrittlement, due to stress corrosion cracking),

exfoliation and delamination of both the packaging and the active

electronic elements. Hermeticity of the packaging material may be

achieved in several ways such as hermetic coatings, etc. However, it is

much simpler and more cost effective if the packaging material is

inherently hermetic subsequent to thermal processing.
















0.280
0.260 Alumina
0.240 Tungsten/Copper
0.220 --Kovar
0.200 -
0.180 -
0.160
0.140 -
<3 0.120 .--,Corning 9641
S Silicon -
0.100 -
0.080 -Corning 7070
[88COR]
0.060 [88COR1
0.040 -
0.020-
0 -
0 50 100 150 200 250 300 350 400 450 500

Temperature (C)




























Figure 1.13 Thermal expansion of Si and other selected materials
as a function of temperature [88COR,90GEI,91DIL]








37

This is accomplished in most ceramic and glass materials when sintered

to more than approximately 95% of theoretical density [76KIN].

Adequate mechanical properties and high thermal conductivity are

also desirable in electronic packaging materials. Since mechanical

failure is frequently due to CTE mismatch or improper thermal treatment,

this problem can be avoided by careful design and processing.

Frequently, it is becoming more important that the green package have

greater green strength, in order to avoid damage during processing.

Packaging design evolution also has moved away from using the

electronic package as a supporting or structural member for the

apparatus. Conventional wisdom more frequently dictates that it is

better if the package provides support and protection only for the

elements that it packages. This further reduces mechanical requirements

of the electronic packaging material. However, a minimal mechanical

strength is still desirable. The materials utilized in the IBM TCM

currently have a bending strength of about three quarters of that of

Al203 (i.e. -210 MPa) [91KUM1,91KUM2,91SHE2,91TUM], while other

institutions have decided that lower strengths are permissible

[89EMU,89SAW,90RIC,91ALE,etc.].

Indeed, if ceramic materials are to be continued in use as

dielectric insulating materials in high performance electronic packages,

K will have to decrease, necessitating that composites of ceramic and

either polymer materials or porosity be used in the future. This will

surely decrease the mechanical strength of said materials [91KUM]. In

the future, the consequences of using lower strength packaging materials

will be circumvented through proper package design and processing as

well as careful materials selection.

High thermal conductivity is no longer as important a material

attribute either, since ingenious designs now remove generated heat from

the back of the chip instead of through the substrate [82BLO,83BLO,

89SER,89TUM3,91TUM].










This method is advantageous in several ways. First, since heat removal

through the back of the IC chip is quite amenable to active cooling

technologies, a much greater amount of heat may be dispersed through its

use. Also, removal of heat through the substrate is generally regarded

as an inferior method since it requires that the heat flux traverse the

metallizations and chip bonding materials. This increases thermal

stresses while reducing electrical conductivity. Also, with continued

decreases in conductor scale (i.e. reduction in the size of chip-package

interconnections), thermal conductivity would be further retarded. This

effect can be offset only through the utilization of thermal vias, which

are very costly in terms of IC chip "real estate."

Removal of heat, through the substrate, to a thermal sink rather

than to a cold finger on top of the chip, also results in thermal

resistances which are significantly greater than in the cold finger

method unless ultra high thermal conductivity materials (i.e. diamond,

or cubic BN) are used. The Franz-Weiderman rule [83POB] indicates that

this technique is not useful in high performance packaging applications

where a low dielectric constant is also required (with a few notable

exceptions such as diamond, cubic BN, or BeO, etc.). The Franz-

Weiderman principle states that no material may have both an ultra high

thermal conductivity as well as a low dielectric constant. The

exceptions to this rule are either prohibitively expensive or toxic.

Furthermore, there are no exceptions to the Franz-Weiderman rule when it

is necessary to select materials having a K below 5.5. Since, in high

speed electronic applications, satisfactory dielectric properties are

most important, the material designer must prioritize on the side of low

dielectric constant, low dielectric loss materials.

High thermal conductivity is also important from a thermal shock

point of view since a high thermal conductivity promotes heat spreading

throughout the package, thus reducing thermal fluctuations within the

package. However, as stated in section 1.3.3, use of a high thermal









conductivity material in conjunction with a through-the-substrate

cooling mechanism will actually reduce the solder-package interface

temperature, thereby increasing the thermally induced shear stresses on

the solder pads (relative to use of a lower thermal conductivity

material in the same heat removal configuration).

It should be noted that the development of a successful packaging

candidate (i.e. one which satisfies the above packaging criteria)

requires a two-pronged, holistic approach. Both materials selection and

packaging design are extremely important in achieving the criteria

discussed above. Furthermore, there is no one package that satisfies

all the requirements in all systems. In some cases, mechanical

integrity or hermeticity is the most important characteristic, while in

others, signal processing is tantamount. Therefore, no one design or

material is universally satisfactory to all electronic packaging

applications. Furthermore, pursuing more than one of the above

packaging criteria, requires skillful design as well as use of

engineered (i.e. composite) materials. Therefore, it is of extreme

importance to decide what packaging criteria are most important when

developing packaging materials or designs for a specific application or

family of applications. Table 1.1 can help to serve as a guide in

packaging design and materials selection.

This study attempts to present a viable packaging material system

that satisfies the materials-based (not design-based) factors of the

packaging criteria outlined above. Furthermore, the greatest importance

is placed upon a materials solution which emphasizes signal processing

speed (i.e. low dielectric loss materials), adjustability for varying

application (i.e. composite materials), and cost reduction (i.e. low

materials cost, applicability to traditional processing, and thermal

processability at reduced temperatures (low temperature cofirability))

while exhibiting environmental stability (i.e. hermeticity and at least

a minimum mechanical strength). It is the author's opinion that these










are the most important packaging criteria for the advancement of high

speed electronic computing.



1.4 Materials Solutions to Electronic Packaging Problems

1.4.1 Ceramics versus Polymers

Nearly 85% of all electronic packages currently produced are

polymer based while ceramic packages comprise approximately two thirds

of the monetary value of the electronic packaging market [89TUM3]. So-

called plastic packaging systems are based on some type of insulating

polymer encapsulant such as epoxy, polyimide, silicone, or, of late,

thermoplastics [89TUM3]. They offer several advantages over ceramic

systems such as lower cost, lower dielectric constant, and greater ease

and adaptability of manufacture as well as greater relative throughput.

Seemingly these advantages would mandate that all electronic packages be

polymer-based. However, the use of plastic packaging systems has

several disadvantages. Table 1.2 shows the advantages and disadvantages

of ceramic versus plastic electronic packaging materials.

Currently, no plastic package is truly hermetic although materials

are being developed which are less hydrophilic than traditional

polymeric packaging materials (i.e. polyquinolines, teflons, and BCBs)

[90LEE,90REC,91HEN,91HOR,91ZUS]. Therefore, the packaging thickness

must be carefully controlled in order to allow some of the moisture,

present within the package, to be evaporatively removed using IC chip

heating (89TUM3]. If the electronic device is one that consumes very

little power (i.e. dissipates very little heat), such as CMOS

devices,special packaging design considerations are mandated.

Furthermore, plastic packaging materials have a much greater CTE than

the materials which they encapsulate (i.e. Si). Resultant thermal

stresses may damage delicate microcircuitry. This requires

implementation of careful package design and manufacturing principles.










Table 1.2

Advantages and Disadvantages in the Polymeric
versus Ceramic Electronic Packaging Materials Debate


Topic Ceramic Polymeric Advantage

Adaptability to Moderate Moderate Depends
Multilayer Packaging (Usually
Ceramic)

Cost High Low Polymer

Breakdown Voltage High High Depends

Dielectric Constant Moderate Low Polymer

Dielectric Loss Low Low Depends
(Usually
Polymer)

Ease of Process Low High Polymer
Automation

Hermeticity Hermetic Non-Hermetic Ceramic

Inherent a--Radiation Variable Variable Depends
(Usually
Ceramic)

Process Complexity High Low Polymer

Process Temperature High Low Polymer

Process Throughput Moderate High Polymer

Rigidity High Flexible Ceramic

Strength High Flexible Depends
(Usually
Ceramic)

Surface Smoothness Moderate High Depends
(Usually
Polymer)

Tolerance Control and High Low Ceramic
Reproducibility

Thermal Conductivity High Low Ceramic

Thermal Expansion Low (Highly High Ceramic
Variable)

Volume Resistivity High High Depends










Plastic packaging materials are characterized by poor thermal

conductivity as well. Due to the encapsulating nature of most plastic

packaging methods used, this factor, when combined with the unfavorably

large CTE of polymers, can be quite deleterious. However, the moisture

evaporation methods used to compensate for a lack of hermeticity help

counteract this problem somewhat (at least in the lower scales of

integration), since evaporation is highly endothermic.

Ceramic packages offer the advantages of hermeticity, CTEs

comparable to switching materials or metallizations, higher thermal

conductivity, and greater integrity. However, ceramics, as a group,

have higher dielectric constants and higher dielectric losses, and are

more susceptible to stress corrosion cracking [89TUM3]. Furthermore it

is difficult and expensive to produce ceramic substrates having

relatively high surface smoothness.

Also disadvantageous to both plastic and ceramic packaging is

inherent alpha radiation that is emitted from trace impurities within

the polymeric and ceramic raw materials. Inherent a--radiation has been

found to cause spurious semiconductor device switching which results in

soft errors. For example, concentrations of approximately 1.0 ppm U2

or 0.4 ppm Th32 within a plastic or ceramic package would emit a flux of

alpha radiation on the order of 0.1 a/cm2/h. That level of radiation is

one to two orders of magnitude above the acceptable limit established

for memory devices [89TUM3].

This radiation problem is currently remedied by adding anti-

radiation coatings, as well as through improved raw material processing

and careful packaging design. However, these corrections add a great

deal to the packaging cost, (which is the main advantage of using

plastic packages). Furthermore, as the scale and pitch of integration

increase and decrease respectively, a--radiation switching is expected

to become more problematic. Ceramic packaging materials tend to exhibit

this problem to a lesser extent than polymeric materials [89TUM3].







43

However, radiation is a bonafide problem in both, thereby mandating that

electronic packaging materials be very highly refined (at least on the

first packaging level).

Thus, ceramics are used for high performance applications that are

not as cost sensitive as typical consumer electronics while plastic

packages are utilized for lower cost electronics. The disadvantages of

ceramic-based packaging, in the area of dielectric properties, are

currently circumvented through package design (i.e. by using 3--

dimensional, multilayer packages, etc.). For the highest electronic

performance applications, however, plastic-on-ceramic hybrids are

currently used [91KUM1,91KUM2,91SHE2,91TUM]. Porous ceramics and

ceramic-plastic composites are also being developed for use in the

highest performance applications as well [86CRO,86DAS,87KEL,87MOH,

88GER3,88IBR,89JUN,89LEA,89YAM2,90KAT,90STE,91SAC1,91ZUS, etc.].



1.4.2 Methods and Materials

1.4.2.1 Traditional

The history of ceramic electronic packaging is covered in section

1.3.1 above. From the above, it is evident that the evolution of this

field has been mainly design (and not materials) oriented. Most ceramic

electronic packages and packaging systems were established using

alumina-based substrate materials.

However, materials selection has become increasingly important

with the advancement of the field. Materials performance limitations

are currently thought to be the limiting factor to advancement of the

field.

It is of value here to elaborate upon the electronic packaging

system that is described in section 1.3.1 above and is generally

perceived to be the state-of-the-art in ceramic electronic packaging.

This system is IBM's thermal conduction module (TCM). The TCM

originally was an alumina-based multilayer package for the IBM 3081










computer system. The original package provided power, cooling and

signal integration to more than 100 ICs. The original TCM was a

"vertical" design, having 33 ceramic layers interconnected by vias. Due

to the relatively high processing temperatures of the original TCM, the

conductor metallurgy was based upon "refractory" metal (i.e. tungsten or

molybdenum based).

The TCM introduced a very advanced cooling system based upon

water-chilled cold fingers, enclosed within a helium-filled chamber,

that connected directly to the back of the thermal conductive-paste-

covered Si chips. This design made excellent use of C4 or flip chip

technology.

The IBM TCM has evolved over its 10+ year life span. The current

TCM (produced for use in the IBM system 390/9000), is glass-ceramic-

based and has copper metallization. It has 63 dielectric layers and

exhibits vastly improved performance. Table 1.3 delineates the

differences between one of the alumina-based TCMs (used in the IBM

system 3090, ca. 1986) and the latest generation of its evolution.

The process for producing the TCM is outlined in Figure 1.9 above.

The basic process has not changed except that the thermal processing

treatment now includes a crystallization step.

The thermal conduction module is not the only advanced ceramic

electronic packaging system in use today. Some other systems are the

liquid-cooled-module (LCM) of NEC, Fujitsu's double-sided board (DSB)

system, and Hitachi's card on board (COB) system. These systems, and

others, are elaborated upon in various literature sources [89SER,89TUM3,

etc]. These systems all would benefit (or have benefitted) through the

use of low dielectric loss, cofirable ceramic packaging materials.



1.4.2.2 Advanced

The subject of advanced electronic packaging is very large and

there are several excellent publications which cover the subject










Table 1.3

The IBM Thermal Conduction Module
Then and Now [91TUM]


Substrate IBM System 3090 IBM System 390/ES9000
Characteristic Alumina/Molybdenum Glass-Ceramic/Copper
(ca. 1986) (ca. 1991)

Size (mm) 110.5 x 117.7 127.5 x 127.5
Number of Layers 45 63

Number of Vias 4.7 x 105 2 x 106
(Total)
Wiring Density 450 844
(cm/cm3)
Line Width (pm) 100 75

Via Diameter (pm) 125 90 and 100

Dielectric Constant 9.4 5.0

Resistivity (pn-cm) 11 3.5

CTE (RT to 200C) 60 30
(ppm)
Shrinkage Control +0.15 +0.1
(%)










[89SER,89TUM3]. Table 1.4 is a comprehensive condensation of recent

research performed in the field of advanced ceramic electronic

packaging. Data on polymers and metals are also included. Because of

the considerable length of Table 1.4, it is placed at the end of Chapter

One.

The subject of advanced ceramic packaging may be divided into

three general processing categories: thin film, thick film and tape

cast processing. Thin films (in this context) may be produced by

several means including thermal evaporation, and sputter deposition,

etc. Thick films (in this context) are deposited by screen printing and

may be used for both insulation and metallization. Tape casting is

currently the most used method for producing high performance electronic

packaging. Thin film technology offers the advantages of producing

comparatively smaller size structures (thinner layers and narrower

lines) and thus will become most important in the future. Thin films

characteristically have a smoother surface structure than thick films,

thereby allowing advanced metallization techniques (i.e.

photolithography, e-beam lithography, etc.) to be used. Currently the

minimum line width feasible using thin film and optical lithography is

approximately 0.5 pm [91CAL].

Thick film materials typically do not display the surface

smoothness required for lithography processes and thus minimum line

widths are currently limited to approximately 25 to 50 pm [90STE].

However, with the use of smaller particle sizes and improved processing

technology, ceramic photolithography has also become the subject of

investigation [90NEB]. The thickness (or thinness) of thick film layers

is similarly limited. In the future, both types of packages will

involve multilayered structures almost exclusively.

Furthermore, as mentioned in section 1.4.1 above, polymer-on-ceramic

hybrid multilayer structures (similar to those used in the most current

IBM TCM) will become very popular.










Metal coated ceramic substrate materials also fit into the

category of advanced electronic packaging due to their novelty,

toughness, tailorable thermal expansion, high thermal conductivity and

low dielectric constant, as a group [81HAN,86SAT,86TEA,870KA,87SHU].

However, multilayer structures have not yet been produced by this method

and, therefore, they are limited to special applications. Generally,

ceramic coatings are deposited over metal bases by either

electrophoretic or thick film deposition techniques. These composites

will see limited future use in such applications as automotive

electronics as well as other high temperature, high stress, corrosive

environment applications.

From a materials point of view, advanced electronic packaging

materials fall into one of two categories: polymer or ceramic. It

should be noted that, in this discussion, polymer materials, are carbon-

based, organic materials and not ceramic, sol-gel processed materials.

The advantages and disadvantages of both types of materials are defined

in section 1.4.1.1 above. Generally, polymers are utilized in advanced

thin or thick film multilayer structures while ceramics are used to

produce advanced thick film or tape cast multilayer packages.

Current polymer materials research for electronic packaging

applications is centered mainly in two areas: developing low moisture

absorbing polymers, and developing polymeric or polymeric-ceramic

materials having thermal expansions matching either Si or GaAs. Thus

far, teflons, polyquinolines, and bisbenzocyclobutenes (BCBs) have shown

promise as reduced water absorption materials [90REC,91HEN,91ZUS] while

composites of epoxy/Kevlar, epoxy/Nextel, polyimide/Kevlar, and

polyimide/glass have shown promise as matched thermal expansion

materials [88IBR,91ZUS].

Recently, research in the area of advanced ceramic electronic

packaging materials has investigated several, varied topics. Low

temperature cofirability (allowing the use of low p (resistivity)










metallization) has been a universal trend in almost all of this

research. Advanced ceramic electronic packaging materials research may

be further divided into the categories of diamond films [91LYN],

glass+ceramics, glass-ceramics, and porous ceramics. Table 1.4, placed

at the end of this chapter, provides a condensation of materials and

processing information for all of these areas, as well as a bibliography

for the convenience of the reader. Diamond thin films have not yet been

successfully implemented for use in high speed microelectronic

packaging, due mainly to the infancy of the field.

Glass+ceramic and glass-ceramic materials are currently the

mainstay of the high performance electronic packaging field. However,

no ceramic material that is a viable future high speed electronic

packaging candidate has a dielectric constant below 3.78 [76KIN]. It

has been stated that electronic materials used in future high

performance packaging applications will necessarily have dielectric

constants below this value [86CRO,87MOH,87YAR,88GIL etc.]. Therefore,

the only way to achieve dielectric constant values below 3.78 while

using ceramic materials, is to fabricate composites of ceramic materials

with non-ceramic, electronically insulating materials, that have lower

dielectric constants (i.e. polymers, or air). The decisive majority of

this research has been in the area of porous ceramics.

Cofirable, porous ceramic materials may be produced from glass,

glass+ceramics or glass-ceramics and are, thus, considered a subset of

each group. Porous ceramics may be produced in several ways. Porous

ceramic thin films may be produced by partial densification of SiO2 sol-

gel films [86CRO,87MOH,88MOH], thermal oxidation of sputtered columnar

Si (86DAS], and reactive sputtering of Si02 [86DAS], as well as by

suspension of latex in silica sol [87MOH]. These methods have not yet

been implemented in electronic packaging, however, due to poor film

hermeticity as well as inadequate mechanical properties and surface

smoothnesses, etc.










Porous thick films have been produced by addition of hollow silica

glass microspheres (HGMS) [87KEL,89LEA,89JUN,90KEL], partial sintering

of glass frit pastes [90WAH], and controlled gas generation within fully

dense glass thick films [90STE,90WAH]. These methods have found greater

success. However, problems with surface smoothness necessitate extra

thick film applications with sealing pastes. Furthermore, the

repetition inherent in thick film processing limits the applicability of

the thick film process in general, since only one layer may be produced

at one time. Finally, the controlled gas generation method involves a

large volume expansion, and thus, dimensional stability becomes a

problem in multilayer structures containing porosity produced via

controlled gas generation. However, this method has been utilized to

produce metallization lines as narrow as 25 to 50 pm in a single layer

configuration [90STE].

It is not sufficient simply to add porosity to the insulating

material. In order to maintain a hermetic structure, porosity must be

non-continuous. Furthermore, the porosity must be small in order to

maintain surface smoothness as well as mechanical properties. While

surface roughness improves interlayer and metallization adhesion, it is

detrimental when the scale of said roughness is within approximately one

tenth of the smallest signal line dimension. Roughness on this scale

not only increases the possibility of electrical discontinuity of signal

traces, but promotes inhomogeneity of the signal trace cross section.

This is highly detrimental at high frequencies since it causes

inhomogeneities in the characteristic impedance (Zo). Furthermore,

variances in cross section force high frequency electronic signals

through a relatively tortuous path. This not only increases signal

propagation distance, but increases spurious signal reflection [89TYL).

Finally, it is best if included porosity be limited to as small a volume

fraction as possible in order to preserve dielectric breakdown strength,










volume resistivity, surface smoothness, sinterability, mechanical

properties and thermal conductivity, etc.

Currently, tape casting is the only feasible method by which

porous ceramic materials have been produced for electronic packaging.

Porosity has been introduced into tape cast ceramics via hollow silica

glass microspheres (HGMs) [88LEA1] as well as through the controlled

burnout and subsequent differential sintering of organic latex

microspheres (89YAM2,90KAT].

The HGM method allows for a greater amount of included porosity to

be added to the packaging material than the latex method, since the

added porosity, resultant from HGM additions, is non-continuous.

Therefore, the HGM method is better in theory and is the only currently

viable method for producing tape cast packaging materials having greater

than -13V% non-continuous porosity. However, the only successfully

produced and tested ultra low dielectric permittivity, multilayer

electronic packages produced, to date, have utilized the latex method

[89YAM2,90KAT]. There are several reasons for this. First, HGMs are

comparatively quite large (-80 Mm) and thus promote surface roughness.

Also, HGMs have very low density (-0.25 g/cm3 [89LEA]) and thus tend to

segregate during suspension processing. Third, HGMs tend to break down

during processing (such as pressing, laminating, sonic dismembrating,

etc.). Finally, as HGMs become smaller, it will become necessary to add

them to the ceramic matrix in larger amounts (compared to latex) due to

the wall thickness of HGMs. For example, pores resulting from the

burnout of latex and subsequent sintering of the surrounding matrix tend

to comprise a volume similar to the volume of the latex spheres which

formed them. With HGMs, however, the amount of SiO2 added to the

ceramic matrix per microsphere addition may, in fact, be similar to, or

greater than the amount of porosity added. An HGM having a diameter of

5 pm and a wall thickness of 0.5 pm is only 51% porous itself. Said HGM

would have a K of -2.4 (as compared to -1 for air). In this scenario,










the HGM method would be much less efficient for reduction of K than the

latex method. Since it is desirable to add a minimum of either HGM

(mainly for sinterability and mechanical integrity reasons) or latex

(mainly for hermeticity and mechanical integrity reasons), the latex

method is preferable in this sense.

Hermetic ceramic materials having dielectric constants as low as

3.4 have been produced, via tape casting, and utilized in multilayer

packages in the laboratory (89YAM2,90KAT]. Commercial introduction of

such a product has not yet occurred, however.

Therefore, it is imperative that further research be performed in

the area of controlled porosity ceramics for utilization in ultra high

speed electronic packaging. Many materials and processing related

questions remain in this field. Research in this area should focus upon

methods to minimize (and the theories involving minimization of)

dielectric constant and dielectric loss while maintaining a hermetic

material of dimensional and mechanical adequacy.



1.5 Proposed Packaging Material System: Statement of Thesis

1.5.1 Choice of Electronic Packaging Material System

The choice of the electronic packaging material system to

investigate was based upon creating a relatively low cost, hermetic,

ceramic packaging material for use in very high speed electronic

packaging applications. From the above criteria, it becomes apparent

that no one material is satisfactory for this application. Therefore,

it was decided to chose a composite system having carefully selected

constituents. This methodology is useful in that the composite may be

optimized for different applications. Properties of the materials

utilized are outlined in Table 1.4 at the end of this chapter.

Cofireability is obtained by using a borosilicate glass as the composite

matrix. Surface smoothness is also enhanced when a viscous sintering

matrix is used. Low dielectric constant and tan(6) are achieved by










utilization of materials having low K and tan(6) values as well as

through the addition of controlled porosity. Furthermore, all materials

utilized have dielectric properties which are stable over a broad range

of frequencies.

In this study, controlled porosity is achieved via the addition,

and subsequent pyrolysis, of uniform polystyrene latex microspheres

(UPLMs). The UPLMs are producible in a size range between 3 and 9 pm

and are quite monodisperse, thereby allowing a study of the effects of

UPLM size and dispersity upon the hermeticity of the sintered material.

The composite system of focus should also be easily adaptable to

standard ceramic tape casting processes. Since the maximum diameter of

the latex is less than 10 pm, the surface smoothness criterion should

also be satisfied for most current thick film signal line widths (if

proper dispersion and homogenization are achieved).

There are some problems associated with adding porosity to a

brittle material. Porosity in a ceramic material has been shown to

reduce the mechanical strength of said material [76KIN]. Furthermore,

it is possible to create a non-hermetic material from a formerly

hermetic one. Therefore, processing must be optimized to provide

hermetic materials having acceptable mechanical properties.

In order to increase the mechanical integrity of the composite

system, a hard particulate ceramic is added. Since mechanical strength

and toughness must be increased with minimal increase in dielectric

properties, the choices for ceramic filler are limited to strong

particulate ceramic materials having low K and tan(6) (such as diamond,

cubic BN or Si3N4). In order to reduce material costs, particulate Si3N4

was used. Silicon nitride represents the best compromise between

desired properties and expense, thereby making this packaging system

practical for most electronic packaging applications. Also, since the

Si3N4 was used as a nonreactive addition, all information related to

sintering and processed microstructure, gained from this study, should







53

be generally applicable to similar composites with other, similar, inert

additions.

1.5.2 Topics of Investigation

This study investigates several factors crucial to the development

of the proposed borosilicate glass-particulate Si3N4-controlled porosity

composite system. This section outlines the topics of research

investigated in this study.

The following constituent variables are investigated:

the effects of ball milling on the properties of the
borosilicate glass powder

the effects of borosilicate glass size and size distribution
upon sintering behavior of said glass

the effects of UPLM volume fraction, size and size
distribution upon both green and selected sintered materials
properties (see below)

the effects of Si3N4 volume fraction and/or included porosity
volume fraction upon sintering behavior, and selected
sintered materials properties (see below).

The following processing factors are investigated:

the effects of suspension sonication and aging upon green
and non-sintered properties

the effects of pyrolysis/presintering upon borosilicate
glass surface area and surface pore size distribution

the effect of heat treating Si3N4 powder in air, at or above
composite sintering temperatures, upon the properties of
said Si3N4

the effect of sintering temperature upon sintering rate.

The following materials parameters are investigated:

the effect of porosity and Si3N4 volume fraction upon the
dielectric constant of the composite

the effect of frequency upon dielectric properties

the effect of atmospheric exposure upon hermetic and non-
hermetic materials

the effect of porosity and Si3N4 volume fraction upon the
hardness of the composites.









Models of composite materials properties, as well as models

concerning the effect of pore percolation upon hermeticity, the effect

of non-sintering particulate and/or included porosity volume fraction

upon sintering behavior and the effect of porosity upon assorted

mechanical properties (as described in Chapters Two and Four), are

utilized to characterize the composite system. A discussion of the

universal applicability of said experimental results to other analogous

systems is included as well.

The main emphasis of this study, however, is to investigate and

model the phenomena involved in the creation and maximization of closed

porosity, produced using the methods described within, in order to

reduce the dielectric constant of the composite and while providing a

candidate material for MLC applications.










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CHAPTER TWO
THEORETICAL AND TECHNICAL REVIEW


2.1 Overview

This chapter outlines selected theoretical and technical issues

important to this project. The microstructure desired in the porous,

glass+ceramic composite system is illustrated in Figure 2.1. Figure 2.2

outlines the process by which said composites are produced. Figure 2.2

also delineates the important factors involved in each processing step.

The topics that are discussed in this chapter are depicted in bold faced

italic print. The other topics mentioned in Figure 2.2 are not

discussed since it is assumed that the reader has sufficient knowledge

in said areas. Further information may be obtained from the references

accompanying said topics if needed.



2.2 Synthesis and Processing of Uniform Polystyrene Latex
Microspheres (UPLMs)

Spherical particles are currently utilized in several applications

such as printer inks, and time-released drugs, etc. Hollow spherical

particles, as well as organic spherical powders, are also used as

composite components in applications requiring low density, rigid

materials. There are several review articles in the literature on the

subjects of solid spherical fillers [78RYA1] and hollow spherical

fillers [78RYA2,86SMI] as well as composites containing them [85VER].

Due to the reasons outlined in Chapter 1, only uniform polymeric

microspheres were deemed suitable for this project. Furthermore, other

research [89YAM2,90KAT] has revealed that the best uniform polymeric

microspheres for this application are those made of polystyrene.







Microstructure


Figure 2.1


Depiction of the glass+ceramic, controlled porosity
microstructure desired


Key:

SB-S Glass Particle


SLatex UPLM

I 0 Si3N, Particles


Green Microstructure dispersantt omitted)


C. B-S Glass/Si ,N,


A. Pure B-S Glass


D. B-S Glass/Si ,N,/Latex UPLM


B. B-S Glass/Latex UPLM










A. Constituent Powders

1. Glass 2. UPLM 3. Silicon Niti

t 0







D- B. Ball Mill C. Settle and
Batch


D. Suspension Processing
and Casting







E. Green Characterization



-n^-

F. Thermal Processing







G. Characterization


Topics of Research:
A. General:
Density, Size, Size Distribution,
Surface Area, Structure [76KIN,88FUN,
88REE,89DIN,90RIN,90WAR,92SHE]
Al:
Chemistry [88REE]
A2:
Synthesis and Processing
B:
Surface Area, Structure, Chemistry,
Density [76KIN,88REE,91SEA]
C:
Particle Packing


Dispersion Systems,Rheology,
Solids Loading [76KIN,81SCH,88FUN,
88REE,90GOO,90RUY,91HOF,91KUR,
91RUS]

Settling, Segregation
Structural [56FATi,56FAT2,56FAT3,
76KIN,88REE,91 MIK,91 SEA,91TSA]


Fl. Pyrolysis:
Thermogravimetric Analysis,
Differential Thermal Analysis
Pore Structure, Surface Area [76KIN,
88REE,89SER,89TUM3,91TUM]

Pore Percolation, Pore Clustering,
Pore Packing

F2. Viscous Sintering
Sintering Rates, Differential Sintering
Microstructural Evolution
F3. Oxidation
Oxidation of Si3N, Powder [89SOM]
G:
Microstructural [53FUL,68DEH,88REE]
Mechanical
Dielectric


Figure 2.2


Process flow diagram for production of controlled
porosity composites, and delineation of important
factors for each processing step; topics depicted in
boldface italic are discussed in this chapter







78

There are several methods for synthesizing uniform particles. The

literature contains several review articles on the subject

[68STO,80UGE,820VE]. More specifically, there are several methods by

which uniform polystyrene latex microspheres (UPLMs) may be produced

[85LOK,86TSE,88LU,89FER]. More information about the properties and

applications of uniform latex particles is contained within references

87BAN2 and 88MIC as well.

As will be shown in Chapter 4, preliminary research for this

project [90RAN] indicated that the UPLM particles should be

approximately 4 pm (minimally 2 pm) in diameter in order to avoid

producing obscured porosity. Furthermore, it was decided that the

maximum UPLM diameter, used for included porosity, should be less than

10 pm in order to maintain surface smoothness requirements. Therefore,

it was necessary to either find or invent a reliable and reproducible

method for the synthesis of UPLMs in the size range between 2 and 10 pm.

Fortunately, researchers have found synthesis methods which satisfy the

above criteria (85LOK,86TSE,88LU]. Said synthesis techniques involve

the dispersion polymerization of styrene in EtOH-based solvents.

Dispersion polymerization is the only currently known method which may

be used to produce UPLMs in the size range of interest via a single set

of processing steps [85LOK]. Table 2.1 depicts the differences between

dispersion, emulsion and suspension polymerization methods.

The synthesis methods of Lu et al. and Tseng et al. [86TSE,88LU]

involve dispersion polymerization via an addition polymerization

mechanism in various mixtures of pure EtOH and stabilizer and/or

costabilizer while the method of Lok and Ober [85LOK] involves

dispersion polymerization of UPLMs via an addition polymerization

mechanism in solvent solutions of ethanol and methyl cellosolve mixed

with hydroxypropylcellulose (100,000 mw) as a dispersant.

Preliminary research, investigating both of the aforementioned

dispersion polymerization methods for synthesis of UPLMS, resulted in










Table 2.1

Comparison of the Different Types
of Particle Polymerization [85LOK]


Emulsion Dispersion Suspension

Monomer Droplets Particles Droplets
Micelles/Particles Mostly in Little in Medium
Little in Medium Medium

Initiator Mostly in Medium Particles and Particle/Droplet
Medium

Stabilizer May Be Present Necessary Necessary

Surfactant Present None None

Initial Multiple Phase Single Phase Dual Phase
Homogeneity










the conclusion that the method of Lok and Ober [85LOK] was far superior

for production of UPLMs in the desired size range on the bases of

monodispersity, amount of agglomeration and reproducibility of UPLM size

and dispersity from batch to batch. Therefore, the method of Lok and

Ober was utilized to produce UPLMs of various size for the current

study. The synthesis method of Lok and Ober is described in further

detail in Chapter 3 as well as in 85LOK.

Figure 2.3 illustrates the dispersion polymerization process.

Basically, dispersion polymerization is an addition polymerization which

includes nucleation and growth steps. The dispersity of the process

depends upon the monomer and initiator concentrations as well as on the

dispersive abilities of the dispersant, which is necessarily a graft

copolymer. Dispersion polymerization involves the nucleation and growth

of polymeric spheres from a single phase solvent via addition reaction.

As with other nucleation and growth processes, the size of each polymer

nucleus must surpass a critical radius before said nucleus becomes

stable. The critical nucleus size depends heavily upon the total system

solubility index (including that of the monomer itself) [85LOK].

Furthermore, growth processes apparently occur without further

nucleation (85LOK].

The major difference between dispersion polymerization and other

polymerization methods is that dispersion polymerization starts as

single phase homogeneous system. With dispersion polymerization it is

necessary that the monomer be soluble in the solvent while the polymer

not be soluble in the solvent. Particle size control with the

dispersion polymerization method is dependent mainly upon four factors,

monomer versus polymer solubility, reactant composition, temperature,

and solvent medium [85LOK].

Said process offers the advantage that it does not require

oligomer swelling, etc., in order to obtain the relatively large

particles and, therefore, is denoted a single step process.


































































Figure 2.3


I-; ; 81


INITIATION

AT
Stabilizer


Initiator



I r HYDROGEN
ABSTRACTION


I I

2 ,



GRAFT
S 'I FORMATION

f -Monomer


3 /



I -
NUCLEATION

Monomer
I



\ Monomer
5 '











Schematic illustration depicting nucleation and growth
of a UPLM via dispersion polymerization LOK
4 !




SGROWH I


I -'






Schematic illustration depicting nucreation and growth
of a UPLM via dispersion polymerization [85LOK,










The method of Lok and Ober offers a further advantage in that the

dispersion mechanism used is steric in nature (ie. non-electrostatic)

and, thereby reduces ionic impurities in the resultant UPLMs. Ionic

impurities are deleterious because they could leave ionic residues

subsequent to pyrolysis. These residual ions would increase K as well

as decrease both p and the dielectric breakdown strength.

Lok and Ober were able to produce exceptionally monodisperse

polystyrene latex particles of sizes ranging from 3 to 9 pm by varying

the solution solubility parameter (6) from 11.5 to 11.9 [85LOK]. The

solubility parameter is resultant from an accumulation of dispersion

forces (6,), polar forces (6p), and hydrogen bonding forces (6,)

according to the relation:

82=68+2+6+2




Table 2.2 lists the solubility parameter as well as other pertinent data

of selected dispersant liquids that Lok and Ober used for dispersion

polymerization. Figure 2.4 depicts a ternary composition diagram,

between EtOH, styrene and MeCell (methyl cellosolve), which outlines

the compositions at which their latexes were monodisperse as well as the

sizes of the respective UPLMs.

It is evident, from the above and from Figure 2.4, that the

dispersion polymerization method of Lok and Ober [85LOK] fulfills the

criteria necessary for the UPLMs used in this project. Furthermore,

through judicious mixing of the UPLMs (as described in the next

section), a polydisperse latex could be produced for maximum packing

efficiency (PE), thereby allowing an investigation of the effect of

included pore size distribution, or possibly pore packing, upon included


porosity.













Solubility Parameters of


.e 2.2

Selected Solvents [85LOK]


Solvent Dielectric Dipole 6 6, 6, 6H
Constant Moment (cal/cm3)'l
(K) (D)

Dimethoxy- 8.6
ethane

Tetrahy- 7.32 1.63 9.1 8.2 2.8 3.9
drofuran

Styrene 9.3 9.1 0.5 2.0

Cellosolve 2.08 10.5 7.8 4.5 7.0

t-Butanol 10.9 1.66 10.6

Me Cell 16 2.2 11.4 7.9 4.5 8.0

Isopro- 18.3 1.66 11.5
panol

Ethanol 24.3 1.69 12.7 7.7 4.3 9.5

Methanol 32.6 1.70 14.5 7.4 6.0 10.9

Water 78.5 1.84 23.4 6.0 15.3 16.7

Poly- 2.5 8.9
styrene










Key:
0 Monodisperse


Me Cell


Concentrations (V%)


Sample Styrene EtOH Me Cell Size (pm) 6, (cal/cm)"2


51
71
60
42.5
30
14
40
44
74
67


39
14
25
42.5
55
71
40
30
0
0


Figure 2.4


Ternary illustration depicting the relative dispersity
of UPLMs synthesized via dispersion polymerization in
the EtOH-MeCell-styrene system (85LOK]


Particle


Solubility
Parameter


1-3
1-4
3
7
9
1-50
5-20
5-20
1-5
7-9


11.9
12.1
11.9
11.7
11.5
11.3
11.6
11.5
11.9
11.7











2.3 Particle Packing

2.3.1 Monosized Spheres

2.3.1.1 Ordered Packing

Ordered packing of hard, uniform spheres may occur in five

different configurations: cubic, orthorhombic, tetragonal, pyramidal,

and tetrahedral [88REE]. Figure 2.5 illustrates the various

configurations and properties of said ordered packing configurations.

Table 2.3 depicts some of the characteristics of two types of ordered

packing structures: cubic and tetrahedral.

However, hard spheres do not naturally pack in the long range,

ordered structures characteristic of crystalline materials. Several

researchers have tried to explain the random packing of monosized

spheres in terms of mixtures of the above ordered structures

[29SMI,61MCG,80PAT], but while three-dimensional, packed beds of

monosized spheres may exhibit short range order, or even order

throughout a dimension, (depending upon the packing method, or the

packing container configuration used, etc.) they are essentially

considered to pack in random order over the long range

[60BER,62EPS,65LEV].



2.3.1.2 Random Packing

There are two types of random packing for non-interacting, hard

spheres, random close packing (RCP) and random loose packing (RLP).

Random packing (RP) is defined as packing that has no characteristic

ordering. These two types of random packing are considered to be the

upper and lower limits to the packing efficiency of randomly packed

monosized spheres, and are quite sensitive to both the size and

configuration of the bed container as well as the methods used to place

the spheres, in said container, in their final state. The generally

accepted packing efficiencies for these two types of packing are 64V%

and 60V% for RCP and RLP respectively [60SCO,61MCG].





















2. Orthorhombic
(Single Staggered)


3. Tetragonal
(Double Staggered)


5. Tetrahedral
(Hexagonal Close Packing)


Figure 2.5


4. Pyramidal
(Cubic Close Packing)


Illustration of the five possible types of ordered
packing of monosized hard spheres [80PAT,88REE]


1. Cubic


Packing
I Packing Configuration CN Densit (V%)

1 Cubic 6 52.4

2 Orthorhombic 8 60.5
(Single Staggered)
3 Tetragonal 10 69.8
(Double Staggered)
4 Pyramidal (Cubic 12 74.0
Close Packing) 12
Tetrahedral (Hex-
Sagonal Close Packing) 12 74.0












Table 2.3


Some Parameters of Simple Cubic and Tetrahedral
Uniform Spheres [88REE]


Packings of


Parameter Cubic Tetrahedral

Entry Pore Area 0.21D2 0.04D2

0.26 0.05
En try-Pore-Area
7ED2
4



0.51 0.22
En try-Pore-Diameter
D



0.42 0.15
En try-Sphere-Diame ter 0.42 0.15
D



Void Fraction 0.48 0.26

0.92 0.34
Vol ume- Voids
Vol ume-Spheres



1.37 4.44
DP imary-Sphere
DIntersti tial -Sphere-Si te



D = Sphere Diameter










The upper limit of random packing (RCP) is never reached in reality, due

to packing friction and interaction with the container. The effect of

the container interaction may be significantly reduced by using a

container having a width dimension that is relatively large compared to

the sphere diameter (usually several hundred times larger) as well as

through utilization of containers having walls which are either modified

with indentations, or that have the ability to conform (i.e. balloons,

etc.) [30WES,60SCO,61MCG,69SCO]. Figure 2.6 illustrates the effect of

the relative container size on the packing density of RCP beds of

monosized spheres. The lower limit to random packing of uniform spheres

(RLP) designates the limit below which packed beds cannot support

themselves without either cohesion or adhesion [60SCO,80SHA].

In practice, all randomly packed uniform spherical particles will

exhibit packing efficiencies (PEs) somewhere between the RCP and RLP

limitations. Most research indicates RP packing efficiencies of

approximately 61 to 63 V% for beds formed by tamping [30WES,60SCO,61MCG,

88REE] and approximately 57 to 59 V% for beds formed by careful pouring

[60SCO,62EPS]. This will occur, in packed beds of monosized spheres,

regardless of sphere size, unless surface area to volume ratio sensitive

factors, such as electrostatic repulsion, etc. become significant (i.e.

as in many micron to sub micron particles). In most instances involving

packed beds of uniform spheres, the packing is RCP and the generally

accepted packing efficiency is 62.5 V% [61MCG,88REE].



2.3.2 Packing of Multimodal, Discrete Distributions of Spheres

Furnas is generally believed to have introduced the first packing

model (the Furnas model) which predicts the random close packing of

multimodal beds of spheres [28FUR,31FUR]. Westman and Hugill also

introduced an analogous packing model at about the same time [30WES],

and it is believed that the actual mathematical treatment of Westman and

Hugill actually proceeded that of Furnas by about one year [79FED].
































1 5 10 50 100

D/d ( Container Diameter )
Sphere Diameter )


Figure 2.6


Effect of relative container size upon the packing
efficiency of random close packed uniform spheres
[61MCG]


70


65



60



55



50


0
C
0
c
o(


w
r-
LU

C


0-


45


200